SL811HST-AXC Cypress Semiconductor Corp, SL811HST-AXC Datasheet - Page 29

• Manufacturer Part Number: SL811HST-AXC
• Description: IC USB HOST/SLAVE CTRLR 48LQFP
• Manufacturer: Cypress Semiconductor Corp

Specifications of SL811HST-AXC

• Package / Case: 48-LQFP
• Applications: USB Host/Slave Controller
• Controller Series: USB-Hosts
• Ram Size: 256 x 8
• Interface: USB
• Number Of I /o: 8
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 65°C
• Mounting Type: Surface Mount
• Operating Supply Voltage: 3 V
• Supply Current (max): 25 mA
• Maximum Operating Temperature: + 65 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Core Size: 8 Bit
• Ram Memory Size: 256Byte
• Cpu Speed: 48MHz
• Embedded Interface Type: I2C, USB
• Digital Ic Case Style: TQFP
• Supply Voltage Range: 3V To 3.45V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3662 - KIT DEVELOPMENT EZ-811HS
• Core Processor: -
• Program Memory Type: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-1721; SL811HST-AXC

Document 38-08008 Rev. *D
DMA Read Cycle
Note Data is held until nDACK goes high regardless of state of nREAD.
Reset Timing
Note Clock is 48 MHz nominal.
t
t
RESET
IOACT
tdack
tddrdlo
tdckdr
tdrdp
tdhld
tddaccs
tdrdack
tdakrq
trdcycle
Parameter
Parameter
n D R Q
D 0-D 7
n R D
n D A C K
nRD or nWR
nRst Pulse width
nRst HIGH to nRD or nWR active
nDACK low
nDACK to nRD low delay
nDACK low to nDRQ high delay
nRD pulse width
Date hold after nDACK high
Data access from nDACK low
nRD high to nDACK high
nDRQ low after nDACK high
DMA Read Cycle Time
nRST
Description
tdaccs
Description
treset
S L 811 D M A R E A D C Y C L E T IM IN G
SL811 DMA Read Cycle Timing
Reset Timing
tdckdr
tddrdlo
100 ns
150 ns
90 ns
85 ns
Min.
0 ns
5 ns
5 ns
0 ns
5 ns
tdrdp
16 clocks
16 clocks
tioact
tdack
Min.
D A T A
Typ.
Typ.
tdakrq
tdhld
SL811HS
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Max.
Max.