ATAM862P-TNSY4D Atmel, ATAM862P-TNSY4D Datasheet - Page 76
![IC MCU FLASH 4K TX 433MHZ 24SSOP](/photos/6/76/67636/453-24-ssop_sml.jpg)
ATAM862P-TNSY4D
Manufacturer Part Number
ATAM862P-TNSY4D
Description
IC MCU FLASH 4K TX 433MHZ 24SSOP
Manufacturer
Atmel
Datasheet
1.ATAM862P-TNQY4D.pdf
(110 pages)
Specifications of ATAM862P-TNSY4D
Applications
UHF ASK/FSK
Core Processor
MARC4
Program Memory Type
FLASH (4 kB)
Controller Series
MARC4 4-Bit
Ram Size
256 x 4
Interface
SSI
Number Of I /o
11
Voltage - Supply
1.8 V ~ 4 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
24-SSOP
Processor Series
ATAM862x
Core
MARC4
Data Bus Width
4 bit
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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23.8.5
76
ATAM862-4
9-bit Shift Mode (MCL)
In the 9-bit shift mode, the SSI is able to handle the MCL protocol (described below). It always
operates as an MCL master device, i.e., SC is always generated and output by the SSI. Both the
MCL start and stop conditions are automatically generated whenever the SSI is activated or
deactivated by the SIR bit. In accordance with the MCL protocol, the output data is always
changed in the clock low phase and shifted in on the high phase.
Before activating the SSI (SIR = 0) and commencing an MCL dialog, the appropriate data direc-
tion for the first word must be set using the SDD control bit. The state of this bit controls the
direction of the data port (BP43 or MCL_SD). Once started, the 8 data bits are, depending on
the selected direction, either clocked into or out of the shift register. During the 9th clock period,
the port direction is automatically switched over so that the corresponding acknowledge bit can
be shifted out or read in. In transmit mode, the acknowledge bit received from the device is cap-
tured in the SSI Status Register (TACK) where it can be read by the controller. In receive mode,
the state of the acknowledge bit to be returned to the device is predetermined by the SSI Status
Register (RACK).
Changing the directional mode (TX/RX) should not be performed during the transfer of an MCL
telegram. One should wait until the end of the telegram which can be detected using the SSI
interrupt (IFN =1) or by interrogating the ACT status.
Once started, a 9-bit telegram will always run to completion and will not be prematurely termi-
nated by the SIR bit. So, if the SIR bit is set to ‘1’ in telegram, the SSI will complete the current
transfer and terminate the dialog with an MCL stop condition.
Figure 23-19. Example of MCL Transmit Dialog
(IFN = 0)
(IFN = 1)
Interrupt
Interrupt
SRDY
ACT
SDD
SIR
SD
SC
Write STB
(tx data 1)
Start
msb
7 6 5 4 3 2 1
tx data 1
lsb
0 A
Write STB
(tx data 2)
msb
7 6 5 4 3 2 1 0 A
tx data 2
lsb
Stop
4551G–4BMCU–07/07
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