ADE7569ASTZF16 Analog Devices Inc, ADE7569ASTZF16 Datasheet - Page 138
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ADE7569ASTZF16
Manufacturer Part Number
ADE7569ASTZF16
Description
IC ENERGY METER MCU 16K 64LQFP
Manufacturer
Analog Devices Inc
Specifications of ADE7569ASTZF16
Applications
Energy Measurement
Core Processor
8052
Program Memory Type
FLASH (16 kB)
Controller Series
ADE75xx
Ram Size
512 x 8
Interface
I²C, SPI, UART
Number Of I /o
20
Voltage - Supply
3.135 V ~ 3.465 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LQFP
Ic Function
Single Phase Energy Measurement IC
Supply Voltage Range
3.13V To 3.46V, 2.4V To 3.7V
Operating Temperature Range
-40°C To +85°C
Digital Ic Case Style
LQFP
No. Of Pins
64
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ADE7569ASTZF16
Manufacturer:
AD
Quantity:
310
Company:
Part Number:
ADE7569ASTZF16
Manufacturer:
Analog Devices Inc
Quantity:
10 000
Company:
Part Number:
ADE7569ASTZF16-RL
Manufacturer:
Analog Devices Inc
Quantity:
10 000
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
SPI INTERRUPT AND STATUS FLAGS
The SPI interface has several status flags that indicate the status
of the double-buffered receive and transmit registers. Figure 111
shows when the status and interrupt flags are raised. The transmit
interrupt occurs when the internal serial port shift register is loaded
with the data in the SPI/I2C transmit buffer SFR (SPI2CTx,
Address 0x9A) register. If the SPI master is in transmit
operating mode, and the SPI/I
Address 0x9A) register has not been written with new data by
the beginning of the next byte transfer, the transmit operation
stops.
When a new byte of data is received in the SPI/I
buffer SFR (SPI2CRx, Address 0x9B), the SPI receive interrupt
flag is raised. If the data in the SPI/I
SPICPHA = 0
SPICPHA = 1
2
C transmit buffer SFR (SPI2CTx,
2
C receive buffer SFR
SPITx1 FLAGS
SPITx0 FLAGS
SPIRx1 AND
SPIRx0 AND
(SPICPOL = 1)
SPITx1 FLAGS
SPITx0 FLAGS
(SPICPOL=0)
SPIRx1 AND
SPIRx0 AND
MISO
MOSI
SCLK
SCLK
SS_b
2
MISO
MOSI
C receive
Figure 112. SPI Timing Configurations
MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB
MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB
?
?
Rev. B | Page 138 of 152
MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB
MSB BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 LSB
(SPI2CRx, Address 0x9B) is not read before new data is ready to
be loaded into the SPI/I
Address 0x9B), an overflow condition has occurred. This
overflow condition, indicated by the SPIRxOF flag, forces the
new data to be discarded or overwritten if the RxOFW bit
(SPIMOD1, Address 0xE8) is set.
TRANSMIT SHIFT REGISTER
TRANSMIT SHIFT REGISTER
Figure 111. SPI Receive and Transmit Interrupt and Status Flags
SPITx (EMPTY)
SPITx
STOPS TRANSFER IF TIMODE = 1
SPITxIRQ = 1
2
C receive buffer SFR (SPI2CRx,
?
?
RECEIVE SHIFT REGISTER
RECEIVE SHIFT REGISTER
SPIRx (FULL)
SPIRx
SPIRxOF = 1
SPIRxIRQ = 1