CY8C20636A-24LTXI Cypress Semiconductor Corp, CY8C20636A-24LTXI Datasheet - Page 7
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CY8C20636A-24LTXI
Manufacturer Part Number
CY8C20636A-24LTXI
Description
MCU 8K FLASH 1K SRAM 48VQFN
Manufacturer
Cypress Semiconductor Corp
Series
CapSense® Controllersr
Specifications of CY8C20636A-24LTXI
Program Memory Type
FLASH (8 kB)
Package / Case
48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
Applications
Capacitive Sensing
Core Processor
M8C
Controller Series
CY8C20xx6A
Ram Size
1K x 8
Interface
I²C, SPI
Number Of I /o
36
Voltage - Supply
1.71 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Processor Series
CY8C20x36A
Core
M8C
Data Ram Size
1 KB
Interface Type
I2C, SPI
Maximum Clock Frequency
400 KHz
Number Of Programmable I/os
36
Number Of Timers
3
Operating Supply Voltage
1.71 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
CY3280-20X66
Minimum Operating Temperature
- 40 C
Program Memory Size
8 KB
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Application
CapSense
Processing Unit
Microprocessor
Operating Supply Voltage (min)
1.71V
Operating Supply Voltage (typ)
1.8/2.5/3.3/5V
Operating Supply Voltage (max)
5.5V
Package Type
QFN EP
Pin Count
48
Mounting
Surface Mount
Rad Hardened
No
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
770-1000 - ISP 4PORT FOR CYPRESS PSOC MCU
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY8C20636A-24LTXI
Manufacturer:
CY
Quantity:
110
Part Number:
CY8C20636A-24LTXI
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Designing with PSoC Designer
The development process for the PSoC device differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of user-selectable functions.
The PSoC development process can be summarized in the
following four steps:
Select Components
Both the system-level and chip-level views provide a library of
pre-built, pre-tested hardware peripheral components. In the
system-level view these components are called “drivers” and
correspond to inputs (a thermistor, for example), outputs (a
brushless DC fan, for example), communication interfaces (I
bus, for example), and the logic to control how they interact with
one another (called valuators).
In the chip-level view the components are called “user modules.”
User modules make selecting and implementing peripheral
devices simple, and come in analog, digital, and programmable
system-on-chip varieties.
Configure Components
Each of the components you select establishes the basic register
settings that implement the selected function. They also provide
parameters and properties that allow you to tailor their precise
configuration to your particular application. For example, a Pulse
Width Modulator (PWM) User Module configures one or more
digital PSoC blocks, one for each 8 bits of resolution. The user
module parameters permit you to establish the pulse width and
duty cycle. Configure the parameters and properties to corre-
spond to your chosen application. Enter values directly or by
selecting values from drop-down menus.
Both the system-level drivers and chip-level user modules are
documented in data sheets that are viewed directly in PSoC
Designer. These data sheets explain the internal operation of the
component and provide performance specifications. Each data
sheet describes the use of each user module parameter or driver
property, and other information you may need to successfully
implement your design.
Document Number: 001-54459 Rev. *B
1. Select Components
2. Configure Components
3. Organize and Connect
4. Generate, Verify, and Debug
2
C-
Organize and Connect
You build signal chains at the chip level by interconnecting user
modules to each other and the I/O pins, or connect system-level
inputs, outputs, and communication interfaces to each other with
valuator functions.
In the system-level view selecting a potentiometer driver to
control a variable speed fan driver and setting up the valuators
to control the fan speed based on input from the pot selects,
places, routes, and configures a programmable gain amplifier
(PGA) to buffer the input from the potentiometer, an analog-to-
digital converter (ADC) to convert the potentiometer’s output to
a digital signal, and a PWM to control the fan.
In the chip-level view, you perform the selection, configuration,
and routing so that you have complete control over the use of all
on-chip resources.
Generate, Verify, and Debug
When you are ready to test the hardware configuration or move
on to developing code for the project, you perform the “Generate
Configuration Files” step. This causes PSoC Designer to
generate source code that automatically configures the device to
your specification and provides the software for the system.
Both system-level and chip-level designs generate software
based on your design. The chip-level design provides application
programming interfaces (APIs) with high-level functions to
control and respond to hardware events at run time and interrupt
service routines that you can adapt as needed. The system-level
design also generates a C main() program that completely
controls the chosen application and contains placeholders for
custom code at strategic positions allowing you to further refine
the software without disrupting the generated code.
A complete code development environment allows you to
develop and customize your applications in C, assembly
language, or both.
The last step in the development process takes place inside
PSoC Designer’s Debugger (access by clicking the Connect
icon). PSoC Designer downloads the HEX image to the ICE
where it runs at full speed. PSoC Designer debugging capabil-
ities rival those of systems costing many times more. In addition
to traditional single-step, run-to-breakpoint and watch-variable
features, the debug interface provides a large trace buffer and
allows you to define complex breakpoint events that include
monitoring address and data bus values, memory locations and
external signals.
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