CY7C64713-56LFXC Cypress Semiconductor Corp, CY7C64713-56LFXC Datasheet - Page 36

• Manufacturer Part Number: CY7C64713-56LFXC
• Description: IC MCU USB EZ FX1 16KB 56VQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB FX1™r

Specifications of CY7C64713-56LFXC

• Applications: USB Microcontroller
• Core Processor: 8051
• Program Memory Type: ROMless
• Controller Series: CY7C647xx
• Ram Size: 16K x 8
• Interface: I²C, USB, USART
• Number Of I /o: 24
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C, USART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 3
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• For Use With: 428-1681 - KIT USB FX1 DEVELOPMENT BOARD428-1677 - KIT DEVELOPMENT EZ-USB FX2LP428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 428-1680; CY7C64713-56LFXC

GPIF Synchronous Signals
In the following figure, dashed lines indicate signals with programmable polarity.
The following table provides the GPIF Synchronous Signals Parameters with Internally Sourced IFCLK.
Table 14. GPIF Synchronous Signals Parameters with Internally Sourced IFCLK
The following table provides the GPIF Synchronous Signals Parameters with Externally Sourced IFCLK.
Table 15. GPIF Synchronous Signals Parameters with Externally Sourced IFCLK
Document #: 38-08039 Rev. *F
Notes
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
IFCLK
SRY
RYH
SGD
DAH
SGA
XGD
XCTL
IFCLK
SRY
RYH
SGD
DAH
SGA
XGD
XCTL
15. GPIF asynchronous RDY
16. IFCLK must not exceed 48 MHz.
Parameter
Parameter
IFCLK Period
RDY
Clock to RDY
GPIF Data to Clock Setup Time
GPIF Data Hold Time
Clock to GPIF Address Propagation Delay
Clock to GPIF Data Output Propagation Delay
Clock to CTL
IFCLK Period
RDY
Clock to RDY
GPIF Data to Clock Setup Time
GPIF Data Hold Time
Clock to GPIF Address Propagation Delay
Clock to GPIF Data Output Propagation Delay
Clock to CTL
x
signals have a minimum Setup time of 50 ns when using internal 48-MHz IFCLK.
X
X
to Clock Setup Time
to Clock Setup Time
GPIFADR[8:0]
DATA(output)
DATA(input)
X
X
X
X
Figure 18. GPIF Synchronous Signals Timing Diagram
IFCLK
RDY
CTL
Output Propagation Delay
Output Propagation Delay
X
X
Description
Description
t
SRY
t
SGD
t
XCTL
N
t
XGD
t
IFCLK
valid
t
RYH
t
t
DAH
SGA
N+1
20.83
20.83
Min
Min
8.9
9.2
2.9
3.7
3.2
4.5
0
0
Max
Max
11.5
10.7
200
7.5
6.7
11
15
[15, 16]
[16]
CY7C64713
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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