CY7C64713-56LFXC Cypress Semiconductor Corp, CY7C64713-56LFXC Datasheet - Page 40
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CY7C64713-56LFXC
Manufacturer Part Number
CY7C64713-56LFXC
Description
IC MCU USB EZ FX1 16KB 56VQFN
Manufacturer
Cypress Semiconductor Corp
Series
EZ-USB FX1™r
Datasheet
1.CY7C64713-56LTXC.pdf
(55 pages)
Specifications of CY7C64713-56LFXC
Applications
USB Microcontroller
Core Processor
8051
Program Memory Type
ROMless
Controller Series
CY7C647xx
Ram Size
16K x 8
Interface
I²C, USB, USART
Number Of I /o
24
Voltage - Supply
3.15 V ~ 3.45 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
Data Bus Width
8 bit
Data Ram Size
16 KB
Interface Type
I2C, USART
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
24
Number Of Timers
3
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
For Use With
428-1681 - KIT USB FX1 DEVELOPMENT BOARD428-1677 - KIT DEVELOPMENT EZ-USB FX2LP428-1339 - KIT LOW SPEED PERSONALITY BOARD
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
428-1680
CY7C64713-56LFXC
CY7C64713-56LFXC
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C64713-56LFXC
Manufacturer:
NEC
Quantity:
94
Company:
Part Number:
CY7C64713-56LFXC
Manufacturer:
CYPRESS
Quantity:
717
Part Number:
CY7C64713-56LFXC
Manufacturer:
CYPRESS/赛普拉斯
Quantity:
20 000
Slave FIFO Asynchronous Write
In the following figure, dashed lines indicate signals with programmable polarity.
In the following table, the Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz
Table 21. Slave FIFO Asynchronous Write Parameters with Internally Sourced IFCLK
Slave FIFO Synchronous Packet End Strobe
In the following figure, dashed lines indicate signals with programmable polarity.
The following table provides the Slave FIFO Synchronous Packet End Strobe Parameters with Internally Sourced IFCLK.
Table 22. Slave FIFO Synchronous Packet End Strobe Parameters with Internally Sourced IFCLK
Document #: 38-08039 Rev. *F
t
t
t
t
t
t
t
t
t
WRpwl
WRpwh
SFD
FDH
XFD
IFCLK
SPE
PEH
XFLG
Parameter
Parameter
SLWR Pulse LOW
SLWR Pulse HIGH
SLWR to FIFO DATA Setup Time
FIFO DATA to SLWR Hold Time
SLWR to FLAGS Output Propagation Delay
IFCLK Period
PKTEND to Clock Setup Time
Clock to PKTEND Hold Time
Clock to FLAGS Output Propagation Delay
Figure 23. Slave FIFO Synchronous Packet End Strobe Timing Diagram
SLWR/SLCS#
PKTEND
FLAGS
IFCLK
FLAGS
Figure 22. Slave FIFO Asynchronous Write Timing Diagram
DATA
Description
Description
t
WRpwl
t
SFD
t
XFD
t
t
SPE
FDH
t
WRpwh
t
PEH
t
XFLG
20.83
14.6
Min
Min
50
70
10
10
0
Max
Max
9.5
70
.
CY7C64713
Unit
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Page 40 of 55
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