PNX1501E,557 NXP Semiconductors, PNX1501E,557 Datasheet - Page 280
PNX1501E,557
Manufacturer Part Number
PNX1501E,557
Description
IC MEDIA PROC 266MHZ 456-BGA
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1502EG557.pdf
(828 pages)
Specifications of PNX1501E,557
Applications
Multimedia
Core Processor
TriMedia
Controller Series
Nexperia
Interface
I²C, 2-Wire Serial
Number Of I /o
61
Voltage - Supply
1.14 V ~ 1.26 V
Operating Temperature
0°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
456-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Program Memory Type
-
Ram Size
-
Other names
935274728557
PNX1501E
PNX1501E
PNX1501E
PNX1501E
Available stocks
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Philips Semiconductors
Volume 1 of 1
PNX15XX_SER_3
Product data sheet
Pattern Generation using signal samples
In this type of pattern generation software fills a DMA buffer with sampled values.
Patterns can be generated,
clock input.
The programmed sampling frequency is divided down from an internal 108 MHz clock
using a 16-bit divider. The divider is programmed in the DIVIDER[3:0].FREQ_DIV
fields. The generated clock has a 50% duty cycle if the divider is an even number. In
the case of an odd value the duty cycle is 33-66 or 66-33.
Instead of using the internal 108 MHz clock it is also possible to use one of the
GPIO[6:0] input pins as the pattern generation clock. This is enabled using the bit
fields EN_CLOCK_SEL and CLOCK_SEL in the GPIO_EV[3:0] registers. Some of
these GPIO[6:0] can receive a clock coming from a PNX15xx Series DDS clock
generators, see
clocks need to be turned on by programming the clock module, refer to
Clock
pattern is then generated at the given frequency present on the selected GPIO clock.
GPIO outputs can be grouped together in one FIFO queue. One FIFO queue can
drive 1, 2 or 4 outputs. The number of outputs that can be driven by each queue is
selected by programming GPIO_EV[3:0].EN_IO_SEL. The driven GPIO output pins
are selected by programming the IO_SEL[3:0] registers. The 32-bit sample read from
the DMA buffer is either 32 1-bit samples if 1 output is being driven by the FIFO
Figure 6:
Module. Alternately the clocks can be generated at board level. The signal
1-bit Pattern Generation
Generated
Pattern
Clock
Section
Rev. 3 — 17 March 2006
Sample: 0110....100 read from DMA buffer
2.5. If this feature is used it is important to know that these
Programmed
Frequency
Figure
0
0
1
6, at a programmed frequency or by a selected
1
Chapter 8: General Purpose Input Output Pins
2
1
...
0
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
30
1
PNX15xx Series
31
0
0
Chapter 5 The
8-13
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