AN2131SC Cypress Semiconductor Corp, AN2131SC Datasheet - Page 210

• Manufacturer Part Number: AN2131SC
• Description: IC MCU 8051 8K RAM 24MHZ 44QFP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB®r

Specifications of AN2131SC

• Applications: USB Microcontroller
• Core Processor: 8051
• Program Memory Type: ROMless
• Controller Series: AN213x
• Ram Size: 8K x 8
• Interface: I²C, USB
• Number Of I /o: 16
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 44-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1306; AN2131SC

Bit 5:
To read data over the I
the SCL line. After every eight bits, the master drives SDA low for one clock to indicate
ACK. To signal the last byte of the read transfer, the master floats SDA at ACK time to
instruct the slave to stop sending. This is controlled by the 8051 by setting LastRD=1
before reading the last byte of a read transfer. The I
the end of the transfer (at ACK time).
Bit 4-3:
These bits are set by the boot loader to indicate whether an 8-bit address or 16-bit address
EEPROM at slave address 000 or 001 was detected at power-on. Normally, they are used
for debug purposes only.
Bit 2:
This bit indicates an I
which results when an outside device drives the bus LO when it shouldn’t, or when
another bus master wins arbitration, taking control of the bus. BERR is cleared when
8051 reads or writes the IDATA register.
Bit 1:
Every ninth SCL or a write transfer the slave indicates reception of the byte by asserting
ACK. The EZ-USB controller floats SDA during this time, samples the SDA line, and
updates the ACK bit with the complement of the detected value. ACK=1 indicates
acknowledge, and ACK=0 indicates not-acknowledge. The EZ-USB core updates the
ACK bit at the same time it sets DONE=1. The ACK bit should be ignored for read trans-
fers on the bus.
EZ-USB TRM v1.9
Note
Setting LastRD does not automatically generate a STOP condition. The 8051 should
also set the STOP bit at the end of a read transfer.
LASTRD
ID1,ID0
BERR
ACK
2
2
C bus error. BERR=1 indicates that there was bus contention,
C bus, an I
Last Data Read
Boot EEPROM ID
Bus Error
Acknowledge bit
Chapter 12. EZ-USB Registers
2
C master floats the SDA line and issues clock pulses on
2
C controller clears the LastRD bit at
Page 12-17