AN2131QC Cypress Semiconductor Corp, AN2131QC Datasheet - Page 103

• Manufacturer Part Number: AN2131QC
• Description: IC MCU 8051 8K RAM 24MHZ 80BQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB®r

Specifications of AN2131QC

• Applications: USB Microcontroller
• Core Processor: 8051
• Program Memory Type: ROMless
• Controller Series: AN213x
• Ram Size: 8K x 8
• Interface: I²C, USB
• Number Of I /o: 24
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 80-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1307

The 8051 now loads the next 64 bytes into IN2BUF and then loads the EPINBC register
with 64 for the next two transfers. For the last portion of the transfer, the 8051 loads the
final 28 bytes into IN2BUF, and loads IN2BC with 28. This completes the transfer.
The EZ-USB core takes care of USB housekeeping chores such as handshake verification.
When an endpoint 2-IN interrupt occurs, the user is assured that the data loaded by the
8051 into the endpoint buffer was received error-free by the host. The EZ-USB core auto-
matically checks the handshake information from the host and re-transmits the data if the
host indicates an error by not ACKing.
USB bulk OUT data travels from host to device. The host requests an OUT transfer by
issuing an OUT token to EZ-USB, followed by a packet of data. The EZ-USB core then
responds with an ACK, if it correctly received the data. If the endpoint buffer is not ready
to accept data, the EZ-USB core discards the host’s OUT data and returns a NAK token,
indicating “not ready.” In response, the host continues to send OUT tokens and data to
the endpoint until the EZ-USB core responds with an ACK.
Page 6-6
Initialization Note
When the EZ-USB chip comes out of RESET, or when the USB host issues a bus reset,
the EZ-USB core unarms IN endpoint 1-7 by setting their busy bits to 0. Any IN trans-
fer requests are NAKd until the 8051 loads the appropriate INxBC register(s). The end-
point valid bits are not affected by an 8051 reset or a USB reset. Chapter 10, "EZ-USB
Resets" describes the various reset conditions in detail.
6.5
Bulk OUT Transfers
Chapter 6. EZ-USB CPU
EZ-USB TRM v1.9