AN2136SC Cypress Semiconductor Corp, AN2136SC Datasheet - Page 320

• Manufacturer Part Number: AN2136SC
• Description: IC MCU 8051 8K RAM 24MHZ 44QFP
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB®r

Specifications of AN2136SC

• Applications: USB Microcontroller
• Core Processor: 8051
• Program Memory Type: ROMless
• Controller Series: AN213x
• Ram Size: 8K x 8
• Interface: I²C, USB
• Number Of I /o: 8
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 44-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1309

C.3.4 Mode 2
Mode 2 provides asynchronous, full-duplex communication, using a total of 11 bits: 1 start
bit, 8 data bits, a programmable 9th bit, and 1 stop bit. The data bits are transmitted and
received LSB first. For transmission, the 9th bit is determined by the value in TB8_0 (or
TB8_1). To use the 9th bit as a parity bit, move the value of the P bit (SFR PSW.0) to TB8_0
(or TB8_1).
The mode 2 baud rate is either CLK24/32 or CLK24/64, as determined by the SMOD0 (or
SMOD1) bit. The formula for the mode 2 baud rate is:
Mode 2 operation is identical to the standard 8051.
C.3.4.1
Figure C-13. illustrates the mode 2 transmit timing. Transmission begins after the first roll
over of the divide-by-16 counter following a software write to SBUF0 (or SBUF1). The
UART shifts data out on the TXD0 (or TXD1) pin in the following order: start bit, data bits
(LSB first), 9th bit, stop bit. The TI_0 (or TI_1) bit is set when the stop bit is placed on the
TXD0 (or TXD1) pin.
C.3.4.2
Figure C-14. illustrates the mode 2 receive timing. Reception begins at the falling edge of a
start bit received on the RXD0 (or RXD1) pin, when enabled by the REN_0 (or REN_1) bit.
For this purpose, the RXD0 (or RXD1) pin is sampled 16 times per bit for any baud rate.
When a falling edge of a start bit is detected, the divide-by-16 counter used to generate the
receive clock is reset to align the counter roll over to the bit boundaries.
For noise rejection, the serial port establishes the content of each received bit by a majority
decision of 3 consecutive samples in the middle of each bit time. This is especially true for the
start bit. If the falling edge on the RXD0 (or RXD1) pin is not verified by a majority decision
of 3 consecutive samples (low), then the serial port stops reception and waits for another
falling edge on the RXD0 (or RXD1) pin.
At the middle of the stop bit time, the serial port checks for the following conditions:
C - 24
•
•
RI_0 (or RI_1) = 0, and
If SM2_0 (or SM2_1) = 1, the state of the stop bit is 1.
(If SM2_0 (or SM2_1) = 0, the state of the stop bit doesn’t matter.)
Mode 2 Transmit
Mode 2 Receive
Appendix C: 8051 Hardware Description
Baud Rate =
2
SMODx
64
x
CLK24
EZ-USB TRM v1.9