PIC12F508-I/SN Microchip Technology, PIC12F508-I/SN Datasheet - Page 52

• Manufacturer Part Number: PIC12F508-I/SN
• Description: IC MCU FLASH 512X12 8SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 12Fr

Specifications of PIC12F508-I/SN

• Program Memory Type: FLASH
• Program Memory Size: 768B (512 x 12)
• Package / Case: 8-SOIC (3.9mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Ram Size: 25 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC12F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 25 B
• Interface Type: RS- 232/USB
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 1
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164101, DM163014, DV164120, DM163029
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162059 - HEADER INTRFC MPLAB ICD2 8/14PIN
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Programming (GP3/RB3)/MCLR/V
PIC12F508/509/16F505
7.5
On the PIC12F508/509/16F505 devices, the DRT runs
any time the device is powered up. DRT runs from
Reset and varies based on oscillator selection and
Reset type (see Table 7-6).
The DRT operates on an internal RC oscillator. The
processor is kept in Reset as long as the DRT is active.
The DRT delay allows V
for the oscillator to stabilize.
Oscillator circuits based on crystals or ceramic resona-
tors require a certain time after power-up to establish a
stable oscillation. The on-chip DRT keeps the devices in
a Reset condition for approximately 18 ms after MCLR
has
using an external RC network connected to the MCLR
input is not required in most cases. This allows savings
in cost-sensitive and/or space restricted applications, as
well as allowing the use of the (GP3/RB3)/MCLR/V
pin as a general purpose input.
The Device Reset Time delays will vary from chip-to-
chip due to V
See AC parameters for details.
The DRT will also be triggered upon a Watchdog Timer
time-out from Sleep. This is particularly important for
applications using the WDT to wake from Sleep mode
automatically.
Reset sources are POR, MCLR, WDT time-out and
wake-up on pin change. See Section 7.9.2 “Wake-up
from Sleep”, Notes 1, 2 and 3.
7.6
The Watchdog Timer (WDT) is a free running on-chip
RC oscillator, which does not require any external
components. This RC oscillator is separate from the
external RC oscillator of the (GP5/RB5)/OSC1/CLKIN
pin and the internal 4 MHz oscillator. This means that
the WDT will run even if the main processor clock has
been stopped, for example, by execution of a SLEEP
instruction. During normal operation or Sleep, a WDT
Reset or wake-up Reset, generates a device Reset.
The TO bit (STATUS<4>) will be cleared upon a
Watchdog Timer Reset.
The
programming the configuration WDTE as a ‘0’ (see
Section 7.1 “Configuration Bits”). Refer to the
PIC12F508/509/16F505 Programming Specifications
to determine how to access the Configuration Word.
DS41236E-page 52
reached
WDT
Device Reset Timer (DRT)
Watchdog Timer (WDT)
DD
can
a
, temperature and process variation.
logic
be
DD
permanently
high
to rise above V
(V
PP
IH
as MCLR and
MCLR)
disabled
DD
min. and
level.
PP
by
TABLE 7-6:
7.6.1
The WDT has a nominal time-out period of 18 ms, (with
no prescaler). If a longer time-out period is desired, a
prescaler with a division ratio of up to 1:128 can be
assigned to the WDT (under software control) by
writing to the OPTION register. Thus, a time-out period
of a nominal 2.3 seconds can be realized. These
periods vary with temperature, V
process variations (see DC specs).
Under worst case conditions (V
= Max., max. WDT prescaler), it may take several
seconds before a WDT time-out occurs.
7.6.2
The CLRWDT instruction clears the WDT and the
postscaler, if assigned to the WDT, and prevents it from
timing out and generating a device Reset.
The SLEEP instruction resets the WDT and the post-
scaler, if assigned to the WDT. This gives the maximum
Sleep time before a WDT wake-up Reset.
INTOSC, EXTRC
HS
EC
Note 1:
Configuration
(1)
(1)
Oscillator
, XT, LP
PIC16F505 only.
WDT PERIOD
WDT PROGRAMMING
CONSIDERATIONS
DRT (DEVICE RESET TIMER
PERIOD)
18 ms (typical)
18 ms (typical)
18 ms (typical)
POR Reset
© 2009 Microchip Technology Inc.
DD
= Min., Temperature
DD
18 ms (typical)
and part-to-part
10 μs (typical)
10 μs (typical)
Subsequent
Resets