MC68SEC000AA16 Freescale Semiconductor, MC68SEC000AA16 Datasheet - Page 4

• Manufacturer Part Number: MC68SEC000AA16
• Description: IC MPU 32BIT 16MHZ 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: M68000r

Specifications of MC68SEC000AA16

• Processor Type: M680x0 32-Bit
• Speed: 16MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 64-QFP
• Processor Series: M680xx
• Core: CPU32
• Maximum Clock Frequency: 16 MHz
• Operating Supply Voltage: 3.3 V, 5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Core Size: 32 Bit
• Cpu Speed: 16MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 64
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Frequency Typ: 20MHz
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Clock Frequency: 16MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

4
Address Bus (A23-A0)
This 24-bit, unidirectional, three-state bus can address 16 Mbytes of data. It provides the address for bus
operation during all cycles except interrupt cycles. During interrupt cycles, A3, A2, and A1 reflect the level
of the interrupt being serviced, while A23-A4 and A0 are set to a logic high.
Data Bus (D15-D0)
This 16-bit, bidirectional, three-state bus is the general-purpose data path. Using the mode pin, you can
statically select either 8- or 16-bit modes for data transfer.
Asynchronous Bus Control
Asynchronous data transfers are handled using the following control signals: address strobe (AS), read/
write (R/W), upper and lower data strobes (UDS, LDS), and data transfer acknowledge (DTACK). The
address strobe signal indicates there is a valid address on the address bus. Read/write defines the data bus
transfer as a read or write cycle. The data strobes control the flow of data on the data bus and the data
transfer acknowledge indicates that the data transfer is complete.
Bus Arbitration Control
In multiple bus master systems, the bus arbitration circuit determines which device will be the bus master.
The bus request (BR) indicates that an external device requires bus mastership. A bus grant (BG) indicates
to all other potential bus master devices that the controller will release bus control at the end of the current
bus cycle.
PROCESSOR
STATUS
SYSTEM
CONTROL
Freescale Semiconductor, Inc.
MC68SEC000 PRODUCT INFORMATION
For More Information On This Product,
Figure 2. Functional Signal Groups
GND
RESET
BERR
MODE
V
CLK
HALT
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CC
FC1
FC2
FC0
MC68SEC000
A23-A0
D15-D0
AS
R/W
UDS
LDS
DTACK
IPL0
BR
IPL1
AVEC
BG
IPL2
ADDRESS BUS
DATA BUS
ASYNCHRONOUS
BUS CONTROL
BUS ARBITRATION
CONTROL
INTERRUPT
CONTROL
MOTOROLA