MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 308
MPC8308VMAGD
Manufacturer Part Number
MPC8308VMAGD
Description
MPU POWERQUICC II PRO 473MAPBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MPC8308VMAGD.pdf
(90 pages)
2.MPC8308VMAGD.pdf
(2 pages)
3.MPC8308VMAGD.pdf
(1170 pages)
4.MPC8308VMAGD.pdf
(14 pages)
Specifications of MPC8308VMAGD
Processor Type
MPC83xx PowerQUICC II Pro 32-Bit
Speed
400MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
473-MAPBGA
Product
Network Processor
Data Rate
256 bps
Frequency
400 MHz
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Supply Current (max)
5 uA
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
0 C
Interface
I2C, JTAG, SPI
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Integrated Programmable Interrupt Controller (IPIC)
8.6.5
In addition to the group relative priority option, SICFR[HPI] can be used to specify one interrupt source
as having the highest priority. This interrupt remains within the same interrupt level as the other interrupt
controller interrupts, but is serviced before any other interrupt in
If the highest priority feature is not used, the IPIC selects the interrupt request in MIXA0 to be the highest
priority interrupt and the standard interrupt priority order is used from
updated dynamically to allow the user to change a normally low priority source into a high priority-source
for a period as needed.
8.6.6
Each of the IPIC’s internal and external interrupt sources can independently assert one interrupt request to
the core.
flexibility exists in the relative ordering of the interrupts, but, in general, relative priorities are as shown.
A single interrupt priority number is associated with each table entry.
8-34
•
Spread.
In the spread scheme, priorities are spread over the table so other sources can have lower interrupt
latencies. This scheme is also programmed but cannot be changed dynamically.
Table 8-34
Highest Priority Interrupt
Interrupt Source Priorities
shows the prioritization of these interrupt sources. As described in previous sections,
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
Table 8-34. Interrupt Source Priority Levels
Priority
10
11
12
13
14
15
16
17
18
19
1
2
3
4
5
6
7
8
9
Interrupt Source Description
MIXA0 (Grouped/Spread)
SYSB0 (Grouped)
SYSB1 (Grouped)
SYSB2 (Grouped)
SYSB3 (Grouped)
SYSB4 (Grouped)
SYSB5 (Grouped)
SYSB6 (Grouped)
SYSB7 (Grouped)
MIXA1 (Grouped)
MIXA2 (Grouped)
MIXA3 (Grouped)
MIXB0 (Grouped)
MIXB1 (Grouped)
MIXB2 (Grouped)
MIXB3 (Grouped)
MIXB0 (Spread)
MIXA1 (Spread)
Highest
Table
Table
8-34.
8-34. SICFR[HPI] can be
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