MPC8308VMAGD Freescale Semiconductor, MPC8308VMAGD Datasheet - Page 486
MPC8308VMAGD
Manufacturer Part Number
MPC8308VMAGD
Description
MPU POWERQUICC II PRO 473MAPBGA
Manufacturer
Freescale Semiconductor
Datasheets
1.MPC8308VMAGD.pdf
(90 pages)
2.MPC8308VMAGD.pdf
(2 pages)
3.MPC8308VMAGD.pdf
(1170 pages)
4.MPC8308VMAGD.pdf
(14 pages)
Specifications of MPC8308VMAGD
Processor Type
MPC83xx PowerQUICC II Pro 32-Bit
Speed
400MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
473-MAPBGA
Product
Network Processor
Data Rate
256 bps
Frequency
400 MHz
Supply Voltage (max)
3.6 V
Supply Voltage (min)
3 V
Supply Current (max)
5 uA
Maximum Operating Temperature
+ 105 C
Minimum Operating Temperature
0 C
Interface
I2C, JTAG, SPI
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Enhanced Secure Digital Host Controller
11.4.1
The DMA system address register contains the system memory address used for DMA transfers. Only
access this register when no transactions are executing (after transactions have stopped). The host driver
should wait until PRSSTAT[DLA] is cleared.
Figure 11-3
Table 11-3
11.4.2
The block attributes register configures the number of data blocks and the number of bytes in each block.
Only access this register when no transactions are executing (after transactions have stopped). The host
driver should wait until PRSSTAT[DLA] is cleared. During a data transfer, the following may occur:
Figure 11-4
11-6
Reset
Offset: 0x000
Offset: 0x004 (BLKATTR)
Reset 0
•
•
0–31
Bit
W
W
R
R
Reading this register may return an invalid value.
Writing this register is ignored.
0
0
0
describes the DSADDR fields.
DMA System Address Register (DSADDR)
Block Attributes Register (BLKATTR)
shows the DMA system address register.
shows the DMA system address register.
0
0
DS_ADDR
Name
0
0
0
0
0
0
MPC8308 PowerQUICC II Pro Processor Reference Manual, Rev. 0
DMA system address. When the eSDHC stops a DMA transfer, this register points to the system
address of the next contiguous data position.
Note: The DS_ADDR must be aligned to a four-byte boundary; the two least-significant bits must
0
0
Figure 11-3. DMA System Address Register (DSADDR)
0
0
Figure 11-4. Block Attributes Register (BLKATTR)
BLKCNT
be cleared.
0
0
Table 11-3. DSADDR Field Descriptions
0
0
0
0
0
0
0
0
0
0
0
0
0
0
DS_ADDR
15 16
0
1
0
0
Description
—
0
0
18 19
0
0
0
0
0
0
0
0
0
0
0
0
0
BLKSZE
0
Freescale Semiconductor
0
0
0
0
Access: Read/Write
Access: Read/Write
0
0
0
0
0
0
0
0
31
31
0
0
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