MPC5200CVR400B Freescale Semiconductor, MPC5200CVR400B Datasheet - Page 28

• Manufacturer Part Number: MPC5200CVR400B
• Description: IC MPU 32BIT 400MHZ 272-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC5200CVR400B

• Processor Type: MPC52xx PowerPC 32-Bit
• Speed: 400MHz
• Voltage: 1.5V
• Mounting Type: Surface Mount
• Package / Case: 272-PBGA
• Processor Series: MPC52xx
• Core: e300
• Development Tools By Supplier: MEDIA5200KIT1E
• Maximum Clock Frequency: 400 MHz
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• I/o Voltage: 2.5 V, 3.3 V
• Minimum Operating Temperature: - 40 C
• Core Size: 32 Bit
• No. Of I/o's: 56
• Ram Memory Size: 16KB
• Cpu Speed: 400MHz
• No. Of Timers: 8
• Embedded Interface Type: CAN, I2C, SCI, SPI
• No. Of Pwm Channels: 8
• Digital Ic Case Style: TEPBGA
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1.3.9
The MPC5200B ATA Controller is completely software programmable. It can be programmed to operate with ATA protocols
using their respective timing, as described in the ANSI ATA-4 specification. The ATA interface is completely asynchronous in
nature. Signal relationships are based on specific fixed timing in terms of timing units (nanoseconds).
ATA data setup and hold times, with respect to Read/Write strobes, are software programmable inside the ATA Controller. Data
setup and hold times are implemented using counters. The counters count the number of ATA clock cycles needed to meet the
ANSI ATA-4 timing specifications. For details, see the ANSI ATA-4 specification and how to program an ATA Controller and
ATA drive for different ATA protocols and their respective timing. See the MPC5200B User’s Manual (MPC5200BUM).
The MPC5200B ATA Host Controller design makes data available coincidentally with the active edge of the WRITE strobe in
PIO and Multiword DMA modes.
28
AD[31,27] (wr)
AD[30:28] (wr)
AD[26:25] (wr)
AD[24:0] (wr)
AD[31:0] (rd)
•
•
PCI CLK
Write data is latched by the drive at the inactive edge of the WRITE strobe. This gives ample setup time beyond that
required by the ATA-4 specification.
Data is held unchanged until the next active edge of the WRITE strobe. This gives ample hold time beyond that
required by the ATA-4 specification.
ACK
R/W
ALE
CSx
ATA
OE
TS
t
1
t
10
Address tenure
Address latch
Address[7:31]
Bank[0:1] bits
TSIZ[0:2] bits
t
7
Figure 13. Timing Diagram—MUXed Mode
MPC5200B Data Sheet, Rev. 4
t
14
t
2
t
3
t
8
Data tenure
t
Data
Data
Data
Data
12
t
9
t
15
t
16
t
5
Data
t
t
6
t
11
4
Freescale Semiconductor
t
13