MPC8540PX667LB Freescale Semiconductor, MPC8540PX667LB Datasheet - Page 7

• Manufacturer Part Number: MPC8540PX667LB
• Description: IC MPU 32BIT 667MHZ 783-FCPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8540PX667LB

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 667MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• For Use With: MPC8548CDS - DEV TOOLS CDS FOR 8548MPC8540ADS-BGA - BOARD APPLICATION DEV 8540CWH-PPC-8540N-VE - KIT EVAL SYSTEM MPC8540
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

3 MPC8540 Architecture Overview
The following sections describe the major functional units of the MPC8540.
3.1 e500 Core Overview
The MPC8540 uses the e500 microprocessor core complex. The e500 core has an internal PLL that allows
independent optimization of the operating frequencies. The core frequencies are derived from either the primary PCI
clock input or an external oscillator. For information regarding the e500 core refer to the following documents:
The following is a brief list of some of the key features of the e500 core complex:
Freescale Semiconductor
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— Burstiness feature that permits counting of burst events with a programmable time between bursts
— Triggering and chaining capability
— Ability to generate an interrupt on overflow
System access port
— Uses JTAG interface and a TAP controller to access entire system memory map
— Supports 32-bit accesses to configuration registers
— Supports cache-line burst accesses to main memory
— Supports large block (4-Kbyte) uploads and downloads
— Supports continuous bit streaming of entire block for fast upload and download
IEEE 1149.1-compliant, JTAG boundary scan
783 FC-PBGA package
EREF: A Reference for Freescale Semiconductor Book E and the e500 Core
PowerPC e500 Core Complex Reference Manual
PowerPC e500 Application Binary Interface User's Guide
Implements full Book E 32-bit architecture
Implements additional instructions, registers, and interrupts defined by APUs. The SPE provides an
extensive instruction set for 64-bit vector integer, single-precision floating-point, and fractional operations.
The SPFP APU provides scalar (32-bit) single-precision, floating-point instructions.
The e500 defines features that are not implemented on the MPC8540. It also
generally defines some features that the MPC8540 implements more specifically.
An understanding of these differences can be critical to ensure proper operation.
These differences are summarized in Section 5.14, “MPC8540 Implementation
Details,” in the MPC8540 Integrated Processor Reference Manual.
MPC8540 PowerQUICC III™ Integrated Host Processor Product Brief, Rev. 0.1
NOTE
MPC8540 Architecture Overview
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