MPC8541EVTAPF Freescale Semiconductor, MPC8541EVTAPF Datasheet - Page 50

IC MPU POWERQUICC III 783-FCPBGA

MPC8541EVTAPF

Manufacturer Part Number
MPC8541EVTAPF
Description
IC MPU POWERQUICC III 783-FCPBGA
Manufacturer
Freescale Semiconductor
Series
PowerQUICC IIIr
Datasheets

Specifications of MPC8541EVTAPF

Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
833MHz
Voltage
1.2V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Core Size
32 Bit
Program Memory Size
64KB
Cpu Speed
833MHz
Digital Ic Case Style
BGA
No. Of Pins
783
Supply Voltage Range
1.14V To 1.26V
Rohs Compliant
Yes
Family Name
MPC85XX
Device Core
PowerQUICC III
Device Core Size
32b
Frequency (max)
833MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
1.2V
Operating Supply Voltage (max)
1.26V
Operating Supply Voltage (min)
1.14V
Operating Temp Range
0C to 105C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
783
Package Type
FCBGA
For Use With
MPC8548CDS - DEV TOOLS CDS FOR 8548CWH-PPC-8540N-VE - KIT EVAL SYSTEM MPC8540
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Lead Free Status / Rohs Status
Compliant

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I2C
Figure 35
12 I
This section describes the DC and AC electrical characteristics for the I
12.1
Table 39
50
At recommended operating conditions with OV
Input high voltage level
Input low voltage level
Low level output voltage
Output fall time from V
capacitance from 10 to 400 pF
Pulse width of spikes which must be suppressed by the
input filter
Input current each I/O pin (input voltage is between 0.1 ×
OV
Capacitance for each I/O pin
Notes:
1. Output voltage (open drain or open collector) condition = 3 mA sink current.
2. C
3. Refer to the MPC8555E PowerQUICC™ III Integrated Communications Processor Reference Manual for information on the
4. I/O pins obstruct the SDA and SCL lines if OV
digital filter used.
DD
B
= capacitance of one bus line in pF.
and 0.9 × OV
MPC8541E PowerQUICC™ III Integrated Communications Processor Hardware Specification, Rev. 4.2
2
provides the DC electrical characteristics for the I
I
C
provides the test access port timing diagram.
External Clock
2
C DC Electrical Characteristics
TDI, TMS
DD
JTAG
TDO
TDO
(max)
IH
Parameter
(min) to V
t
Output Data Valid
JTKLOX
IL
(max) with a bus
Figure 35. Test Access Port Timing Diagram
Table 39. I
DD
of 3.3 V ± 5%.
t
VM
JTKLOZ
VM = Midpoint Voltage (OV DD /2)
t
JTKLOV
DD
2
C DC Electrical Characteristics
is switched off.
Symbol
t
t
I2KLKV
I2KHKL
V
V
V
C
OL
I
IH
IL
t
I
I
JTIVKH
2
C interface of the MPC8541E.
20 + 0.1 × C
0.7 × OV
Output Data Valid
–0.3
Min
–10
Data Valid
0
0
Input
VM
DD
B
2
C interface of the MPC8541E.
0.3 × OV
0.2 × OV
OV
Max
DD
250
t
50
10
10
JTIXKH
+ 0.3
DD
DD
Freescale Semiconductor
Unit
μA
pF
ns
ns
V
V
V
Notes
1
2
3
4

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