MC7447AHX1000NB Freescale Semiconductor, MC7447AHX1000NB Datasheet - Page 15
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MC7447AHX1000NB
Manufacturer Part Number
MC7447AHX1000NB
Description
IC MPU RISC 1000MHZ 360-FCCBGA
Manufacturer
Freescale Semiconductor
Datasheet
1.MC7447AVS733NB.pdf
(56 pages)
Specifications of MC7447AHX1000NB
Processor Type
MPC74xx PowerPC 32-Bit
Speed
1.0GHz
Voltage
1.1V
Mounting Type
Surface Mount
Package / Case
360-FCCBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MC7447AHX1000NB
Manufacturer:
Freescale
Quantity:
29
Company:
Part Number:
MC7447AHX1000NB
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Figure 3
Freescale Semiconductor
At recommended operating conditions. See
Processor core frequency
VCO frequency
SYSCLK frequency
SYSCLK cycle time
SYSCLK rise and fall time
SYSCLK duty cycle measured at
OV
SYSCLK cycle-to-cycle jitter
Internal PLL relock time
Notes:
1. Caution: The SYSCLK frequency and PLL_CFG[0:4] settings must be chosen such that the resulting SYSCLK (bus)
2. Assumes a lightly-loaded, single-processor system.
3. Rise and fall times for the SYSCLK input measured from 0.4 to 1.4 V.
4. Timing is guaranteed by design and characterization.
5. Guaranteed by design.
6. The SYSCLK driver’s closed loop jitter bandwidth should be less than 1.5 MHz at –3 dB.
7. Relock timing is guaranteed by design and characterization. PLL relock time is the maximum amount of time required
8. Caution: If DFS is enabled, the SYSCLK frequency and PLL_CFG[0:4] settings must be chosen such that the
9. Caution: These values specify the maximum processor core and VCO frequencies when the device is operated at
frequency, processor core frequency, and PLL (VCO) frequency do not exceed their respective maximum or minimum
operating frequencies. Refer to the PLL_CFG[0:4] signal description in
PLL_CFG[0:4] settings.
for PLL lock after a stable V
applies when the PLL has been disabled and subsequently re-enabled during sleep mode. Also note that HRESET
must be held asserted for a minimum of 255 bus clocks after the PLL relock time during the power-on reset sequence.
resulting processor frequency is greater than or equal to the minimum core frequency.
the nominal core voltage. If operating the device at the derated core voltage, the processor core and VCO frequencies
must be reduced. See
DD
/2
provides the SYSCLK input timing diagram.
SYSCLK
Characteristic
MPC7447A RISC Microprocessor Hardware Specifications, Rev. 5
Section 5.3, “Voltage and Frequency Derating,”
DD
V
and SYSCLK are reached during the power-on reset sequence. This specification also
M
t
Table
KHKL
Figure 3. SYSCLK Input Timing Diagram
Table 8. Clock AC Timing Specifications
Symbol
f
t
t
t
SYSCLK
SYSCLK
SYSCLK
KR
t
KHKL
f
t
f
VCO
SYSCLK
4.
core
, t
KF
/
V
M
1200 2000 1200 2533 1200 2667 1200 2840 MHz
V
Min
600
6.0
1000 MHz
33
40
—
—
—
M
= Midpoint Voltage (OV
1000
Max
Maximum Processor Core Frequency
167
150
100
1.0
30
60
V
M
Min
600
6.0
1267 MHz
33
40
—
—
—
CV
IL
1267
Max
167
150
100
1.0
30
60
for more information.
Section 9.1.1, “PLL Configuration,”
CV
DD
t
Min
600
6.0
1333 MHz
KR
/2)
33
40
IH
—
—
—
Electrical and Thermal Characteristics
1333
Max
167
150
100
1.0
30
60
Min
600
6.0
1420 MHz
33
40
—
—
—
1420 MHz 1, 8, 9
Max
167
150
100
1.0
30
60
t
KF
MHz 1, 2, 8
Unit Notes
ns
ns
ps
μs
%
for valid
1, 9
5, 6
2
3
4
7
15