MPC8260AZUPJDB Freescale Semiconductor, MPC8260AZUPJDB Datasheet - Page 49

• Manufacturer Part Number: MPC8260AZUPJDB
• Description: IC MPU POWERQUICC II 480-TBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC IIr

Specifications of MPC8260AZUPJDB

• Processor Type: MPC82xx PowerQUICC II 32-bit
• Speed: 300MHz
• Voltage: 2V
• Mounting Type: Surface Mount
• Package / Case: 480-TBGA
• Core Size: 32 Bit
• Program Memory Size: 32KB
• Cpu Speed: 300MHz
• Embedded Interface Type: I2C, MII, SPI, TDM, UTOPIA
• Digital Ic Case Style: TBGA
• No. Of Pins: 480
• Rohs Compliant: No
• For Use With: MPC8260ADS-TCOM - BOARD DEV ADS POWERQUICC II
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Freescale Semiconductor
Revision
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 2.0
11/2001
11/2001
8/2003
1/2003
5/2002
3/2002
3/2002
2/2002
8/2001
Date
—
Initial version
• Note: In revision 0.3, sp30
• Removal of “HiP4 PowerQUICC II Documentation” table. These supplemental specifications have
•
• Addition of
• Addition of VCCSYN to “Note: Core, PLL, and I/O Supply Voltages” following
• Addition of note 1 to
•
• Addition of notes or modifications to
•
• Addition of
• Addition of note 2 to
•
•
•
•
•
•
•
•
•
•
•
•
•
•
• Note 2 for
•
•
•
• Section 2.1: Removal of “Warning” recommending use of bootstrap diodes. They are not needed.
•
•
• Note 2 for
• Addition of note at beginning of Section 3.2
• Note 1 for
•
• Revision of
• Modifications to
• Modification to pinout diagram,
• Additional revisions to text and figures throughout
•
“Document Revision History” Table.
been replaced by revision 1 of the MPC8260 PowerQUICC II™ Family Reference Manual .
Figure 1
Table
Table
Table
addition of SPICLK to PC19. They are documented correctly in the parallel I/O ports chapter in the
MPC8260 PowerQUICC II™ Family Reference Manual but had previously been omitted from
Table
Table
Table
Table
Figure
Figure
Table
Section 1,
Section 1,
Table
Table
Table
Table
Table
Table
to 0011_100 and 1011_000 to 1011_1000
Table
Table
Table
Table
Table
Table
Table 23. Document Revision History (continued)
4: Changes to θ
9: Change of sp10.
21: Addition of FCC2 Rx and Tx [3,4] to CPM pins PD7, PD18, PD19, and PD29. Also, the
21.
2: Modification to supply voltage ranges reflected in notes 2, 3, and 4.
4: Addition of θ
7,
14,
2: Note 2 (changes in italics): “... less than or equal to 233 MHz, 166 MHz CPM...”
2: Addition of note 3.
21: Modified notes to pins AE11 and AF25.
21: Modified notes to pins AE11 and AF25.
21: Addition of note to pins AA1 and AG4 (Therm0 and Therm1).
19: Core and bus frequency values for the following ranges of MODCK_HMODCK: 0011_000
21: Notes added to pins at AE11, AF25, U5, and V4.
1: note 3
9: Change to sp12.
10: Change to sp32.
21: Additions to B27, C28, D25, D27, E26, G29, H26–28, N25, P29, AF25, AA25, AB27
8: Change to sp20/sp21.
3,
5,
Figure
and
Figure
Figure
Table
Table 2
Table 16
Table 18
“Features”: minimum supported core frequency of 150 MHz
“Features”: updated performance values (under “Dual-issue integer core”)
Figure 2
Table
Table
Section 1,
8: Addition of sp42a/sp43a.
17, and
Figure
4: Addition of note for FCC output.
6,
15.
5, “Power Dissipation”
(changes in italics): “...greater than or equal to 266 MHz, 200 MHz CPM...”
Figure
and
and
Table 3
Table 21
JB
JA
9,
and θ
Table
“Features”: Addition of MPC8255 notes
Table 17
Table 19
and θ
Table 2,Table
(Table
7: Addition of notes.
JC
19: Removal of PLL bypass mode from clock tables.
JB
.
Figure 13
and θ
10) was changed. This change was not previously recorded in this
Substantive Changes
Figure
JC
10,
.
6,
Table
Figure
11, and
7, and
Table 18
Figure 8
Document Revision History
Table 2
49