MPC852TZT100A Freescale Semiconductor, MPC852TZT100A Datasheet - Page 42

• Manufacturer Part Number: MPC852TZT100A
• Description: IC MPU POWERQUICC 100MHZ 256PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC852TZT100A

• Processor Type: MPC8xx PowerQUICC 32-Bit
• Speed: 100MHz
• Voltage: 1.8V
• Mounting Type: Surface Mount
• Package / Case: 256-PBGA
• Processor Series: MPC8xx
• Core: MPC8xx
• Data Bus Width: 32 bit
• Development Tools By Supplier: MPC852TADS-KIT
• Maximum Clock Frequency: 100 MHz
• Operating Supply Voltage: 1.8 V, 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Family Name: MPC8xx
• Device Core: PowerQUICC
• Device Core Size: 32b
• Frequency (max): 100MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.8/3.3V
• Operating Supply Voltage (max): 1.9/3.465V
• Operating Supply Voltage (min): 1.7/3.135V
• Operating Temp Range: 0C to 95C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

IEEE 1149.1 Electrical Specifications
Figure 35
13 IEEE 1149.1 Electrical Specifications
Table 15
42
Num
J82
J83
J84
J85
J86
J87
J88
J89
J90
J91
J92
J93
J94
J95
J96
TCK cycle time
TCK clock pulse width measured at 1.5 V
TCK rise and fall times
TMS, TDI data setup time
TMS, TDI data hold time
TCK low to TDO data valid
TCK low to TDO data invalid
TCK low to TDO high impedance
TRST assert time
TRST setup time to TCK low
TCK falling edge to output valid
TCK falling edge to output valid out of high impedance
TCK falling edge to output high impedance
Boundary scan input valid to TCK rising edge
TCK rising edge to boundary scan input invalid
DSCK, DSDI
provides the JTAG timings for the MPC852T shown in
provides the reset timing for the debug port configuration.
CLKOUT
SRESET
MPC852T PowerQUICC™ Hardware Specifications, Rev. 4
Figure 35. Reset Timing—Debug Port Configuration
Characteristic
Table 15. JTAG Timing
R80
R70
R81
Figure 36
R82
R80
100.00
100.00
40.00
25.00
40.00
50.00
50.00
through
0.00
5.00
0.00
Min
—
—
—
—
—
All Frequencies
R81
Figure
Freescale Semiconductor
10.00
27.00
20.00
50.00
50.00
50.00
Max
—
—
—
—
—
—
—
—
—
39.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns