MPC885ZP80 Freescale Semiconductor, MPC885ZP80 Datasheet - Page 22

• Manufacturer Part Number: MPC885ZP80
• Description: IC MPU POWERQUICC 80MHZ 357PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC885ZP80

• Processor Type: MPC8xx PowerQUICC 32-Bit
• Speed: 80MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 357-PBGA
• For Use With: CWH-PPC-885XN-VX - BOARD EVAL QUICCSTART MPC885CWH-PPC-885XN-VE - BOARD EVAL QUICCSTART MPC885
• Features: -

Bus Signal Timing
22
B32a
B32b
B32d
B33a
B34a
B34b
B35a
B35b
Num
B32c
B32
B33
B34
B35
CLKOUT falling edge to BS valid, as requested by
control bit BST4 in the corresponding word in the
UPM (MAX = 0.00 × B1 + 6.00)
CLKOUT falling edge to BS valid, as requested by
control bit BST1 in the corresponding word in the
UPM, EBDF = 0 (MAX = 0.25 × B1 + 6.80)
CLKOUT rising edge to BS valid, as requested by
control bit BST2 in the corresponding word in the
UPM (MAX = 0.00 × B1 + 8.00)
CLKOUT rising edge to BS valid, as requested by
control bit BST3 in the corresponding word in the
UPM (MAX = 0.25 × B1 + 6.80)
CLKOUT falling edge to BS valid, as requested by
control bit BST1 in the corresponding word in the
UPM, EBDF = 1 (MAX = 0.375 × B1 + 6.60)
CLKOUT falling edge to GPL valid, as requested
by control bit GxT4 in the corresponding word in
the UPM (MAX = 0.00 × B1 + 6.00)
CLKOUT rising edge to GPL valid, as requested
by control bit GxT3 in the corresponding word in
the UPM (MAX = 0.25 × B1 + 6.80)
A(0:31), BADDR(28:30), and D(0:31) to CS valid,
as requested by control bit CST4 in the
corresponding word in the UPM
(MIN = 0.25 × B1 – 2.00)
A(0:31), BADDR(28:30), and D(0:31) to CS valid,
as requested by control bit CST1 in the
corresponding word in the UPM
(MIN = 0.50 × B1 – 2.00)
A(0:31), BADDR(28:30), and D(0:31) to CS valid,
as requested by CST2 in the corresponding word
in UPM (MIN = 0.75 × B1 – 2.00)
A(0:31), BADDR(28:30) to CS valid, as requested
by control bit BST4 in the corresponding word in
the UPM (MIN = 0.25 × B1 – 2.00)
A(0:31), BADDR(28:30), and D(0:31) to BS valid,
as requested by BST1 in the corresponding word
in the UPM (MIN = 0.50 × B1 – 2.00)
A(0:31), BADDR(28:30), and D(0:31) to BS valid,
as requested by control bit BST2 in the
corresponding word in the UPM
(MIN = 0.75 × B1 – 2.00)
Characteristic
MPC885/MPC880 PowerQUICC Hardware Specifications, Rev. 7
Table 9. Bus Operation Timings (continued)
13.30 18.00 11.30 16.00 7.60 12.30 4.49 11.30
13.20
20.70
13.20
20.70
1.50
7.60 14.30 6.30 13.00 3.80 10.50 3.13 10.00
1.50
7.60 14.30 6.30 13.00 3.80 10.50 3.13 10.00
1.50
7.60 14.30 6.30 13.00 3.80 10.50 3.13 10.00
5.60
5.60
Min
33 MHz
Max
6.00
8.00
6.00
—
—
—
—
—
—
10.50
16.70
10.50
16.70
1.50
1.50
1.50
4.30
4.30
Min
40 MHz
Max
6.00
8.00
6.00
—
—
—
—
—
—
1.50
1.50
1.50
1.80
5.60
9.40
1.80
5.60
9.40
Min
66 MHz
Max
6.00
8.00
6.00
—
—
—
—
—
—
Freescale Semiconductor
1.50
1.50
1.50
1.13
4.25
6.80
1.13
4.25
7.40
Min
80 MHz
Max
6.00
8.00
6.00
—
—
—
—
—
—
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns