MPC8260AZUPIBB Freescale Semiconductor, MPC8260AZUPIBB Datasheet - Page 22

• Manufacturer Part Number: MPC8260AZUPIBB
• Description: IC MPU POWERQUICC II 480-TBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC IIr

Specifications of MPC8260AZUPIBB

• Processor Type: MPC82xx PowerQUICC II 32-bit
• Speed: 300MHz
• Voltage: 2V
• Mounting Type: Surface Mount
• Package / Case: 480-TBGA
• Core Size: 32 Bit
• Program Memory Size: 32KB
• Cpu Speed: 300MHz
• Embedded Interface Type: I2C, MII, SPI, TDM, UTOPIA
• Digital Ic Case Style: TBGA
• No. Of Pins: 480
• Rohs Compliant: No
• For Use With: MPC8260ADS-TCOM - BOARD DEV ADS POWERQUICC II
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -

Electrical and Thermal Characteristics
Table 12
22
JTAG external clock frequency of operation
JTAG external clock cycle time
JTAG external clock pulse width measured at 1.4V
JTAG external clock rise and fall times
TRST assert time
Input setup times
Input hold times
Output valid times
Output hold times
JTAG external clock to output high impedance
1
2
3
4
5
6
7
All outputs are measured from the midpoint voltage of the falling/rising edge of t
in question. The output timings are measured at the pins. All output timings assume a purely resistive 50-Ω load.
Time-of-flight delays must be added for trace lengths, vias, and connectors in the system.
The symbols used for timing specifications herein follow the pattern of t
(reference)(state)
t
(V) relative to the t
timing (JT) with respect to the time data input signals (D) went invalid (X) relative to the t
going to the high (H) state. Note that, in general, the clock reference symbol representation is based on three letters
representing the clock of a particular functional. For rise and fall times, the latter convention is used with the
appropriate letter: R (rise) or F (fall).
TRST is an asynchronous level sensitive signal. The setup time is for test purposes only.
Non-JTAG signal input timing with respect to t
Non-JTAG signal output timing with respect to t
Guaranteed by design.
Guaranteed by design and device characterization.
MPC8260A PowerQUICC™ II Integrated Communications Processor Hardware Specifications, Rev. 2.0
JTDVKH
lists the JTAG timings.
symbolizes JTAG device timing (JT) with respect to the time data input signals (D) reaching the valid state
The UPM machine outputs change on the internal tick determined by the
memory controller programming; the AC specifications are relative to the
internal tick. Note that SDRAM and GPCM machine outputs change on
CLKin’s rising edge.
for inputs and t(
JTG
Parameter
clock reference (K) going to the high (H) state or setup time. Also, t
(first two letters of functional block)(reference)(state)(signal)(state)
Boundary-scan data
Boundary-scan data
Boundary-scan data
Boundary-scan data
Boundary-scan data
Table 12. JTAG Timings
TMS, TDI
TMS, TDI
TCLK
TDO
TDO
TDO
TCLK
.
.
NOTE
t
Symbol
JTGR
t
t
t
t
t
t
t
t
t
t
t
JTDXKH
JTDVKH
JTKHKL
JTKLDV
JTKLOV
JTKLDX
JTKLOX
JTKLDZ
JTKLOZ
JTIVKH
JTIXKH
t
t
TRST
f
t
JTGF
JTG
JTG
and
2
1
Min
(first two letters of functional block)(signal)(state)
40
20
25
10
10
—
—
0
0
4
4
1
1
1
1
TCLK
Max
25
25
25
25
25
—
—
—
—
—
—
—
—
—
for outputs. For example,
5
to the midpoint of the signal
JTDXKH
JTG
clock reference (K)
Freescale Semiconductor
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
symbolizes JTAG
Notes
3, 6
4, 7
4, 7
4, 7
4, 7
5, 7
5. 7
5, 7
5, 7
5, 6
5, 6
—
—
—
6