EZ80L92AZ050SC00TR Zilog, EZ80L92AZ050SC00TR Datasheet - Page 121
![IC EZ80 MPU 100LQFP](/photos/6/76/67664/269-100-lqfp_sml.jpg)
EZ80L92AZ050SC00TR
Manufacturer Part Number
EZ80L92AZ050SC00TR
Description
IC EZ80 MPU 100LQFP
Manufacturer
Zilog
Datasheet
1.EZ80L92AZ020SG.pdf
(231 pages)
Specifications of EZ80L92AZ050SC00TR
Processor Type
eZ80
Features
High Speed, Single-Cycle Instruction-Fetch
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
EZ80L92AZ050SC00T
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PS013014-0107
UART Line Control Registers
This register is used to control the communication control parameters. See
Table
Table 60. UART Line Control Registers (UART0_LCTL = 00C3h, UART1_LCTL =
Bit
Position
2
CLRTXF
1
CLRRXF
0
FIFOEN
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
7
DLAB
61.
00D3h)
Value Description
Value Description
0
1
0
1
0
1
0
1
No effect.
Clear the transmit FIFO and reset the transmit FIFO pointer.
Valid only if the FIFO is enabled.
No effect.
Clear the receive FIFO, clear the receive error FIFO, and reset
the receive FIFO pointer. Valid only if the FIFO is enabled.
Transmit and receive FIFOs are disabled. Transmit and receive
buffers are only 1 byte deep.
Transmit and receive FIFOs are enabled.
R/W
Access to the UART registers at I/O addresses UARTx_RBR,
UARTx_THR, and UARTx_IER is enabled.
Access to the Baud Rate Generator registers at I/O addresses
UARTx_BRG_L and UARTx_BRG_H is enabled.
7
0
R/W
6
0
R/W
5
0
Universal Asynchronous Receiver/Transmitter
R/W
4
0
R/W
3
0
Product Specification
R/W
2
0
eZ80L92 MCU
Table 60
R/W
1
0
R/W
and
0
0
115
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