EZ80L92AZ050SC00TR Zilog, EZ80L92AZ050SC00TR Datasheet - Page 141
![IC EZ80 MPU 100LQFP](/photos/6/76/67664/269-100-lqfp_sml.jpg)
EZ80L92AZ050SC00TR
Manufacturer Part Number
EZ80L92AZ050SC00TR
Description
IC EZ80 MPU 100LQFP
Manufacturer
Zilog
Datasheet
1.EZ80L92AZ020SG.pdf
(231 pages)
Specifications of EZ80L92AZ050SC00TR
Processor Type
eZ80
Features
High Speed, Single-Cycle Instruction-Fetch
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
EZ80L92AZ050SC00T
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PS013014-0107
Table 70. SPI Baud Rate Generator Register—High Byte (SPI_BRG_H = 00B9h)
SPI Control Register
This register is used to control and setup the serial peripheral interface. The SPI must be
disabled prior to making any changes to CPHA or CPOL. See
Table 71. SPI Control Register (SPI_CTL = 00BAh)
Bit
Reset
CPU Access
Note: R/W = Read/Write.
Bit
Position
[7:0]
SPI_BRG_H
Bit
Reset
CPU Access
Note: R = Read Only; R/W = Read/Write.
Bit
Position
7
IRQ_EN
6
5
SPI_EN
4
MASTER_EN
00h–FFh These bits represent the High byte of the 16-bit Baud Rate
Value
Value Description
0
1
0
0
1
0
1
R/W
R/W
SPI system interrupt is disabled.
SPI system interrupt is enabled.
Reserved.
SPI is disabled.
SPI is enabled.
When enabled, the SPI operates as a slave.
When enabled, the SPI operates as a master.
7
0
7
0
Description
Generator divider value. The complete BRG divisor value is
returned by {SPI_BRG_H, SPI_BRG_L}.
R/W
R
6
0
6
0
R/W
R/W
5
0
5
0
R/W
R/W
4
0
4
0
R/W
R/W
3
0
3
0
Table
Product Specification
Serial Peripheral Interface
R/W
R/W
71.
2
0
2
1
eZ80L92 MCU
R/W
R
1
0
1
0
R/W
R
0
0
0
0
135
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