Z8018010FEC Zilog, Z8018010FEC Datasheet - Page 75
Z8018010FEC
Manufacturer Part Number
Z8018010FEC
Description
IC Z180 MPU 80QFP
Manufacturer
Zilog
Datasheet
1.Z8018006PSG.pdf
(85 pages)
Specifications of Z8018010FEC
Processor Type
Z180
Speed
10MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
80-QFP
Processor Series
Z8018xx
Core
Z80
Data Bus Width
8 bit
Maximum Clock Frequency
10 MHz
Number Of Timers
2 bit
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 100 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Height
2.8 mm
Length
20 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
4.5 V
Width
14 mm
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
No RoHS Version Available
Available stocks
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Part Number
Manufacturer
Quantity
Price
TRAP Timing—3
Refresh Control Register
Refresh Control Register (RCA: I/O Address = 36h)
PS014004-1106
A
0
–A
18
MREQ
D
0
(A
rd
WR
RD
–D
M1
19
Op Code Undefined
φ
7
)
Mnemonic RCR (Address 36)
The RCR specifies the interval and length of refresh cycles, while enabling or disabling the
refresh function.
REFE: Refresh Enable (bit 7)—
REFE = 1
REFW: Refresh Wait (bit 6)—
duration.
refresh wait cycle (
T
3nd Opcode
Fetch Cycle
1
Figure 72. Refresh Control Register (RCA: I/O Address = 36h)
Undefined
T
Opcode
PC
2
REFE
REFW = 1
enables refresh cycle insertion.
T
3
Figure 71. TRAP Timing—3
T
REFW
1
READ Cycle
Memory
T
2
IX + d, IY + d
7
—
-
TRW
T
causes the refresh cycle to be three clocks in duration by adding a
TP
6
—
T
3
).
T
REFW
i
5
—
T
i
T
4
—
is set to
i
REFW = 0
T
REFE = 0
i
—
3
T
1
rd
REFE
1
Reserved
T
PC-1
during
SP-1
2
Opcode Undefined
2
—
causes the refresh cycle to be two clocks in
PC Stacking
T
disables the refresh controller, while
3
H
is set to
—
1
T
1
RESET
T
Cyc1
SP-2
2
PC-1
0
—
1
T
3
.
Cyc0
L
during
T
Fetch Cycle
1
Opcode
Restart
from 0000h
0000h
T
2
RESET
T
3
Microprocessor Unit
.
Architecture
Z80180
69