Z8018010FEC Zilog, Z8018010FEC Datasheet - Page 77

• Manufacturer Part Number: Z8018010FEC
• Description: IC Z180 MPU 80QFP
• Manufacturer: Zilog

Specifications of Z8018010FEC

• Processor Type: Z180
• Speed: 10MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 80-QFP
• Processor Series: Z8018xx
• Core: Z80
• Data Bus Width: 8 bit
• Maximum Clock Frequency: 10 MHz
• Number Of Timers: 2 bit
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 100 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Height: 2.8 mm
• Length: 20 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 4.5 V
• Width: 14 mm
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: No RoHS Version Available

MMU Common Base Register
MMU Bank Base Register (BBR: I/O Address = 39h)
MMU Bank Base Register (BBR)
MMU Bank Base Register (BBR: I/O Address = 39h)
PS014004-1106
Bit
Bit
CB7
R/W
BB7
R/W
7
4. The refresh address is incremented by one for each successful refresh cycle, not for each
Mnemonic CBR
Address 38
MMU Common Base Register (CBR)—
boundaries) used to generate a 20-bit physical address for Common Area 1 accesses. All bits
of
Mnemonic BBR
Address 39
BBR
address for Bank Area accesses. All bits of
7
CBR
refresh. Independent of the number of missed refresh requests, each refresh bus cycle
uses a refresh address incremented by one from that of the previous refresh bus cycles.
Figure 73. MMU Bank Base Register (BBR: I/O Address = 39h)
Figure 74. MMU Bank Base Register (BBR: I/O Address = 39h)
specifies the base address (on 4-KB boundaries) used to generate a 19-bit physical
R/W
CB6
are reset to
R/W
6
BB6
6
R/W
CB5
R/W
BB5
5
5
0
during
CB4
R/W
BB4
R/W
4
RESET
4
R/W
CB3
.
R/W
3
BB3
3
BBR
R/W
CB2
CBR
R/W
2
BB2
2
are reset to
specifies the base address (on 4-KB
R/W
CB1
R/W
1
BB1
1
0
during
R/W
CB0
R/W
0
BB0
0
Microprocessor Unit
RESET
.
Architecture
Z80180
71