IDT79RC32V332-100DH IDT, Integrated Device Technology Inc, IDT79RC32V332-100DH Datasheet - Page 12
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IDT79RC32V332-100DH
Manufacturer Part Number
IDT79RC32V332-100DH
Description
IC PROC 32BIT CPU 100MHZ 208-QFP
Manufacturer
IDT, Integrated Device Technology Inc
Series
Interprise™r
Datasheet
1.IDT79RC32T332-100DH.pdf
(30 pages)
Specifications of IDT79RC32V332-100DH
Processor Type
RISC 32-Bit
Speed
100MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
208-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Other names
79RC32V332-100DH
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IDT 79RC32332
Mode Bit Settings to Configure Controller on Reset
reset_boot_mode Settings
1900_0000, as required. The RC32332 cold reset-boot mode initialization setting values and mode descriptions are listed below.
mem_addr[22:21] 1:0 MSB (1)
The following table lists the mode bit settings to configure the controller on cold reset.
By using the non-boot mode cold reset initialization mode the user can change the internal register addresses from base 1800_0000 to base
Pin
ejtag_pcst[2:0]
debug_cpu_i_d_n
debug_cpu_ack_n
debug_cpu_ads_n
debug_cpu_dma_n
mem_addr[17]
mem_addr[19:18]
Reset Boot Mode
Pin
2:0 MSB (2)
3
4
5
6
7
9:8 MSB (9)
Mode Bit
Tri-state memory bus and EEPROM bus during coldreset_n assertion
Reserved
PCI-boot mode (pci_host_mode must be in satellite mode) RC32332 will reset
either from a cold reset or from a PCI reset. Boot code is provided via PCI.
Standard-boot mode Boot from the RC32332’s memory controller (typical system).
Table 3 RC32332 reset_boot_mode Initialization Settings
Clock Multiplier
MasterClock is multiplied internally to gener-
ate PClock
EndBit
Reserved
Reserved
TmrIntEn
Enables/Disables the timer interrupt on Int*[5]
Reserved for future use
Boot-Prom Width specifies the memory port
width of the memory space which contains the
boot prom.
Table 2 Boot-Mode Configuration Settings
Description
12 of 30
Description
Value
00
01
10
11
0
1
2
3
4
5
6
7
0
1
0
0
0
1
1
Multiply by 2
Multiply by 3
Multiply by 4
Reserved
Reserved
Reserved
Reserved
Reserved
Little-endian ordering
Big-endian ordering
Enables timer interrupt
Disables timer interrupt
8 bits
16 bits
32 bits
Reserved
Mode Setting
Value Mode Settings
11
10
01
00
Tri-state_bus_mode
PCI_boot_mode
standard_boot_mode
May 4, 2004