IDT79RC32H434-350BCG IDT, Integrated Device Technology Inc, IDT79RC32H434-350BCG Datasheet - Page 6

• Manufacturer Part Number: IDT79RC32H434-350BCG
• Description: IC MPU 32BIT CORE 350MHZ 256-BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: Interprise™r

Specifications of IDT79RC32H434-350BCG

• Processor Type: MIPS32 32-Bit
• Speed: 350MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Other names: 79RC32H434-350BCG

IDT RC32434
PCILOCKN
PCIPAR
PCIPERRN
PCIREQN[3:0]
PCIRSTN
PCISERRN
PCISTOPN
PCITRDYN
General Purpose Input/Output
GPIO[0]
GPIO[1]
GPIO[2]
GPIO[3]
Signal
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
PCI Lock. This signal is asserted by an external bus master to indicate that an
exclusive operation is occurring.
PCI Parity. Even parity of the PCIAD[31:0] bus. Driven by the bus master during
address and write Data phases. Driven by the bus target during the read data
phase.
PCI Parity Error. If a parity error is detected, this signal is asserted by the
receiving bus agent 2 clocks after the data is received.
PCI Bus Request.
In PCI host mode with internal arbiter:
These signals are inputs whose assertion indicates to the internal RC32434
arbiter that an agent desires ownership of the PCI bus.
In PCI host mode with external arbiter:
PCIREQN[0]: asserted by the RC32434 to request ownership of the PCI bus.
PCIREQN[3:1]: unused and driven high.
In PCI satellite mode:
PCIREQN[0]: this signal is asserted by the RC32434 to request use of the PCI
bus.
PCIREQN[1]: function changes to PCIIDSEL and is used as a chip select during
configuration read and write transactions.
PCIREQN[3:2]: unused and driven high.
PCI Reset. In host mode, this signal is asserted by the RC32434 to generate a
PCI reset. In satellite mode, assertion of this signal initiates a warm reset.
PCI System Error. This signal is driven by an agent to indicate an address par-
ity error, data parity error during a special cycle command, or any other system
error. Requires an external pull-up.
PCI Stop. Driven by the bus target to terminate the current bus transaction. For
example, to indicate a retry.
PCI Target Ready. Driven by the bus target to indicate that the current data can
complete.
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: U0SOUT
Alternate function: UART channel 0 serial output.
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: U0SINP
Alternate function: UART channel 0 serial input.
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: U0RTSN
Alternate function: UART channel 0 request to send.
General Purpose I/O.
This pin can be configured as a general purpose I/O pin.
Alternate function pin name: U0CTSN
Alternate function: UART channel 0 clear to send.
Table 1 Pin Description (Part 3 of 6)
6 of 53
Name/Description
January 19, 2006