IDT79RC32H434-350BCG IDT, Integrated Device Technology Inc, IDT79RC32H434-350BCG Datasheet - Page 9

• Manufacturer Part Number: IDT79RC32H434-350BCG
• Description: IC MPU 32BIT CORE 350MHZ 256-BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: Interprise™r

Specifications of IDT79RC32H434-350BCG

• Processor Type: MIPS32 32-Bit
• Speed: 350MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 256-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Other names: 79RC32H434-350BCG

Pin Characteristics
Pin Characteristics
Pin Characteristics
Pin Characteristics
IDT RC32434
Note: Some input pads of the RC32434 do not contain internal pull-ups or pull-downs. Unused inputs should be tied off to appropriate
levels. This is especially critical for unused control signal inputs (such as WAITACKN) which, if left floating, could adversely affect the
RC32434’s operation. Also, any input pin left floating can cause a slight increase in power consumption.
EJTAG_TMS
JTAG_TRST_N
JTAG_TCK
JTAG_TDO
JTAG_TDI
System
CLK
EXTBCV
EXTCLK
COLDRSTN
RSTN
Signal
Type
I/O
O
O
I
I
I
I
I
I
I
EJTAG Mode. The value on this signal controls the test mode select of the
EJTAG Controller. When using the JTAG boundary scan, this pin should be left
disconnected (since there is an internal pull-up) or driven high.
JTAG Reset. This active low signal asynchronously resets the boundary scan
logic, JTAG TAP Controller, and the EJTAG Debug TAP Controller. An external
pull-up on the board is recommended to meet the JTAG specification in cases
where the tester can access this signal. However, for systems running in func-
tional mode, one of the following should occur:
1) actively drive this signal low with control logic
2) statically drive this signal low with an external pull-down on the board
3) clock JTAG_TCK while holding EJTAG_TMS and/or JTAG_TMS high.
JTAG Clock. This is an input test clock used to clock the shifting of data into or
out of the boundary scan logic, JTAG Controller, or the EJTAG Controller.
JTAG_TCK is independent of the system and the processor clock with a nomi-
nal 50% duty cycle.
JTAG Data Output. This is the serial data shifted out from the boundary scan
logic, JTAG Controller, or the EJTAG Controller. When no data is being shifted
out, this signal is tri-stated.
JTAG Data Input. This is the serial data input to the boundary scan logic, JTAG
Controller, or the EJTAG Controller.
Master Clock. This is the master clock input. The processor frequency is a mul-
tiple of this clock frequency. This clock is used as the system clock for all mem-
ory and peripheral bus operations.
Load External Boot Configuration Vector. When this pin is asserted (i.e.,
high) the boot configuration vector is loaded from an externally supplied value
during a cold reset.
External Clock. This clock is used for all memory and peripheral bus opera-
tions.
Cold Reset. The assertion of this signal initiates a cold reset. This causes the
processor state to be initialized, boot configuration to be loaded, and the internal
PLL to lock onto the master clock (CLK).
Reset. The assertion of this bidirectional signal initiates a warm reset. This sig-
nal is asserted by the RC32434 during a warm reset.
Table 1 Pin Description (Part 6 of 6)
9 of 53
Name/Description
January 19, 2006