IDT79RC64T574-200DZ IDT, Integrated Device Technology Inc, IDT79RC64T574-200DZ Datasheet - Page 4

• Manufacturer Part Number: IDT79RC64T574-200DZ
• Description: IC MPU 64BIT EMB 200MHZ 128-QFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT79RC64T574-200DZ

• Processor Type: RISC 64-Bit
• Speed: 200MHz
• Voltage: 2.5V
• Mounting Type: Surface Mount
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: 79RC64T574-200DZ

ferring data between the processor and memory at a peak rate of
1000MB/sec. A boot-time selectable option to run the system interface
as 32-bits wide—using basically the same protocols as the 64-bit
system—is also supported.
processor modes and is a serial interface that operates at a very low
frequency (SysClock divided by 256). This low-frequency operation
allows the initialization information to be kept in a low-cost EPROM;
alternatively, the twenty-or-so bits could be generated by the system
interface ASIC or a simple PAL. The boot-time serial stream is shown in
Table 3.
0
1:4
5:7
8
9:10
Serial
79RC64574™ 79RC64575™
Bit
A boot-time mode control interface initializes fundamental
Description
Reserved
Transmit-data-
pattern.
Bit 4 is MSB
PClock-to-
SysClk-Ratio.
Bit 7 is MSB
Endianness
Non-block write
Mode. Bit 10 is
MSB
Table 3 Boot-time Mode Stream (Page 1 of 2)
64-bit bus width:
0: DDDD
1: DDxDDx
2: DDxxDDxx
3: DxDxDxDx
4: DDxxxDDxxx
5: DDxxxxDDxxxx
6: DxxDxxDxxDxx
7: DDxxxxxxDDxxxxxx
8: DxxxDxxxDxxxDxxx
9-15: Reserved. Must not be selected.
32-bit bus width:
0: WWWWWWWW
1: WWxWWxWWxWWx
2: WWxxWWxxWWxxWWxx
3: WxWxWxWxWxWxWxWx
4: WWxxxWWxxxWWxxxWWxxx
5: WWxxxxWWxxxxWWxxxxWWxxxx
6: WxxWxxWxxWxxWxxWxxWxxWxx
7: WWxxxxxxWWxxxxxxWWxxxxxxWWxxxxxx
8: WxxxWxxxWxxxWxxxWxxxWxxxWxxxWxxx
9-15: Reserved. Must not be selected.
0: 2
1: 3
2: 4
3: 5
4: 6
5: 7
6: 8
7: Reserved
0: Little endian
1: Big endian
00: R4400 compatible
01: Reserved
10: Pipelined-Write-Mode
11: Write-Reissue-Mode
Must be set to 0.
Value & Mode Setting
4 of 28
external reference clocks. The CPU input clock is the bus reference
clock and can be between 33 and 125MHz. An on-chip phase-locked-
loop (PLL) generates the pipeline clock (PClock) through multiplication
of the system interface clock by values of 2,3,4,5,6,7 or 8, as defined at
system reset. This allows the pipeline clock to be implemented at a
significantly higher frequency than the system interface clock. The
RC64574/575 support both single data (one byte through full CPU bus
width) and 8-word block transfers on the SysAD bus.
double the effective write bandwidth. The write re-issue has a repeat
rate of 2 cycles per write. Pipelined writes have the same 2-cycle per
write repeat rate, but can issue an additional write after WrRdy* de-
asserts.
11
12
13:14
15:17
18
19
20:24
25:26
27:256
Serial
Bit
The clocking interface allows the CPU to be easily mated with
The RC64574/575 implement additional write protocols that
TimerIntEn
System Interface
Bus Width.
Drv_Out
Bit 14 is MSB
Write address to
write data delay.
Reserved
Extend
Multiplication
Repeat Rate.
Reserved
System
configuration
identifier.
Reserved
Description
Table 3 Boot-time Mode Stream (Page 2 of 2)
Timer interrupt settings:
0: Enable Timer Interrupt on Int(5)
1: Disable Timer Interrupt on Int(5)
Interface bus width control settings:
0: 64-bit system interface
1: 32-bit system interface
Slew rate control of the output drivers:
10: 100% strength (fastest)
11: 83% strength
00: 67% strength
01: 50% strength (slowest)
From 0 to 7 SysClk cycles:
0: AD...
1: AxD...
2: AxxD...
3: AxxxD...
4: AxxxxD...
5: AxxxxxD...
6: AxxxxxxD...
7: AxxxxxxxD...
User must select ‘0’
Initial setting of the “Fast Multiply” bit.
0: Enable Fast Multiply
1: Do not Enable Fast Multiply
Note: For pipeline speeds >250MHz, this bit must
be set to ‘1’.
User must select ‘0’
Software visible in processorConfig[21:20]
0: Config[21:20] = Mode Bit [25:26]
Must be set to 0.
User must select ‘0’
Value & Mode Setting
December 14, 2001