IDT79RC64T574-200DZ IDT, Integrated Device Technology Inc, IDT79RC64T574-200DZ Datasheet - Page 8

• Manufacturer Part Number: IDT79RC64T574-200DZ
• Description: IC MPU 64BIT EMB 200MHZ 128-QFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT79RC64T574-200DZ

• Processor Type: RISC 64-Bit
• Speed: 200MHz
• Voltage: 2.5V
• Mounting Type: Surface Mount
• Package / Case: 128-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: 79RC64T574-200DZ

79RC64574™ 79RC64575™
Interrupt Interface
Int*(5:0)
NMI*
Initialization Interface
V
ColdReset*
Reset*
ModeClock
ModeIn
JTAG Interface
TDI
TDO
TCK
TMS
TRST*
JTAG32*
JR_V
CC
O
k
Pin Name
cc
I
I
I
I
I
O
I
I
O
I
I
I
I
I
Type
Interrupt
Six general processor interrupts, bit-wise ORed with bits 5:0 of the interrupt register.
Non-maskable interrupt
Non-maskable interrupt, ORed with bit 6 of the interrupt register.
V
When asserted, this signal indicates to the processor that the power supply has been above the Vcc minimum
for more than 100 milliseconds and will remain stable. The assertion of V
sequence.
Cold reset
This signal must be asserted for a power on reset or a cold reset. ColdReset must be de-asserted synchro-
nously with SysClock.
Reset
This signal must be asserted for any reset sequence. It can be asserted synchronously or asynchronously for
a cold reset, or synchronously to initiate a warm reset. Reset must be de-asserted synchronously with
SysClock.
Boot-mode clock
Serial boot-mode data clock output at the system clock frequency divided by two hundred fifty-six.
Boot-mode data in
Serial boot-mode data input.
JTAG Data In
On the rising edge of TCK, serial input data are shifted into either the Instruction register or Data register,
depending on the TAP controller state. An external pull-up resistor is required.
JTAG Data Out
On the falling edge of TCK, the TDO is serial data shifted out from either the instruction or data register. When
no data is shifted out, the TDO is tri-stated (high impedance).
JTAG Clock Input
An input test clock used to shift into or out of the boundary-scan register cells. TCK is independent of the sys-
tem and processor clock with nominal 40-60% duty cycle.
JTAG Command Select
The logic signal received at the TMS input is decoded by the TAP controller to control test operation. TMS is
sampled on the rising edge of TCK. An external pull-up resistor is required.
JTAG Reset
The TRST* pin is an active-low signal used for asynchronous reset of the debug unit, independent of the pro-
cessor logic. During normal CPU operation, the JTAG controller will be held in the reset mode, asserting this
active low pin.
When asserted low, this pin will also tristate the TDO pin. An external pull-down resistor is required.
JTAG 32-bit scan
This pin is used to control length of the scan chain for SysAD (32-bit or 64-bit) for the JTAG mode. When set
to Vss, 32-bit bus mode is selected. In this mode, only SysAD(31:0) are part of the scan chain. When set to
Vcc, 64-bit bus mode is selected. In this mode, SysAD(63:0) are part of the scan chain. This pin has a built-in
pull-down device to guarantee 32-bit scan, if it is left un connected.
JTAG VCC
This pin has an internal pull-down to continuously reset the JTAG controller (if left unconnected) bypassing
the TRst* pin. When supplied with Vcc, the TRst* pin will be the primary control for the JTAG reset.
CC
is OK
Table 5 Pin Descriptions (Page 2 of 2)
8 of 28
Description
CCO
k initiates the initialization
December 14, 2001