IDT79RC32K438-300BB IDT, Integrated Device Technology Inc, IDT79RC32K438-300BB Datasheet - Page 21

• Manufacturer Part Number: IDT79RC32K438-300BB
• Description: IC MPU 32BIT CORE 300MHZ 416-BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: Interprise™r

Specifications of IDT79RC32K438-300BB

• Processor Type: MIPS32 32-Bit
• Speed: 300MHz
• Voltage: 1.3V
• Mounting Type: Surface Mount
• Package / Case: 416-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: 79RC32K438-300BB

Memory Bus - DDR Access
DDRDATA[31:0]
DDRDM[7:0]
DDRDQS[3:0]
DDRADDR[13:0],
DDRBA[1:0],
DDRCASN, DDRCKE,
DDRCSN[1:0],
DDROEN[3:0],
DDRRASN, DDRWEN
1.
2.
3.
IDT 79RC32438
In the DDR data sheet:
Meets DDR timing requirements for DDR 266 SDRAMs with 400 ps remaining margin to compensate for PCB propagation mismatches, which is adequate to guarantee functional
Setup times are calculated as applicable clock period - Tdo max. For example, if the DDR is running at 266MHz, it uses a 133MHz input clock. The period for a 133MHz clock is
timing, provided the RC32438 DDR layout guidelines are followed.
7.5ns. If the Tdo max value is 4.5ns, the T
Calculations for T
clock is only 3.75ns. So, if the max Tdo is 2.7ns, we have 3.75ns minus 2.7ns = 1.05ns for T
for board propagation delays.
Signal
DS
Mem Control Signals
1.
2.
3.
4.
5.
are similar, but since this parameter is taken relative to the DDRDQS signals, which are referenced on both edges, the effective period with a 133MHz input
Tskew_7g = t
Warm reset caused by any of the conditions listed in the Warm Reset section of Chapter 3, Clocking and Initialization, in the RC32438 User Reference
Manual.
The RC32438 tri-states the data bus, MDATA[15:0], and negates all memory control signals.
The RC32438 negates RSTN.
The RC32438 starts driving the data bus, MDATA[15:0], again, but does not sample the RSTN input.
CPU begins executing by taking a MIPS soft reset exception and also starts sampling the RSTN input again.
Symbol
Tskew_7g
MDATA[15:0]
COLDRSTN
Tdo_7m
Tdo_7k
Tdo_7l
Tac
EXTCLK
RSTN
CLK
3
4
2
1
DQSQ;
Referenc
IS
DDRDQSx
DDRDQSx
DDRCKPx
DDRCKPx
e Edge
parameter is 7.5ns minus 4.5ns = 3ns. The DDR spec for this parameter is 1ns, so there is 2ns of slack left over for board propagation.
Tdo_7k = t
Active
1
Tdz_6d
DH
-0.75
200MHz
Min
0.0
1.5
1.5
1.1
, t
2
Table 7 DDR SDRAM Timing Characteristics
Figure 5 Warm Reset AC Timing Waveform
DS;
Tdo_7l = t
>= 4096 CLK clock cycles
Max
0.75
0.9
3.3
3.3
4.5
-0.75
233MHz
Min
0.0
1.1
1.1
1.1
DH
, t
21 of 59
DS;
Max
0.75
0.9
2.9
2.9
4.5
Tac = t
DS
. The DDR data sheet specs a value of 0.5ns for 266MHz, so this leaves 0.55ns slack
-0.75
Deasserted
266MHz
AC;
Min
0.0
0.9
0.9
1.1
3
Tdo_7m = t
4
Max
0.75
0.9
2.7
2.7
4.5
Tzd_6d
(RSTN ignored during this period
to allow pull-up to drive signal high)
>= 4096 CLK clock cycles
IH
-0.75
300MHz
Min
0.0
0.7
0.7
1.1
, t
IS.
FFFF_FFFF
Max
0.75
0.8
2.4
2.4
4.5
Unit
ns
ns
ns
ns
ns
5
Conditions
Active
May 25, 2004
See Figures 6
and 7.
Reference
Diagram
Timing