IDT79RC32K438-300BB IDT, Integrated Device Technology Inc, IDT79RC32K438-300BB Datasheet - Page 29

• Manufacturer Part Number: IDT79RC32K438-300BB
• Description: IC MPU 32BIT CORE 300MHZ 416-BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: Interprise™r

Specifications of IDT79RC32K438-300BB

• Processor Type: MIPS32 32-Bit
• Speed: 300MHz
• Voltage: 1.3V
• Mounting Type: Surface Mount
• Package / Case: 416-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Other names: 79RC32K438-300BB

PCI
PCICLK
PCIAD[31:0],
PCIBEN[3:0],
PCIDEVSELN,
PCIFRAMEN,PCIIR-
DYN, PCILOCKN,
PCIPAR, PCI-
PERRN, PCIS-
TOPN, PCITRDY
PCIGNTN[3:0],
PCIREQN[3:0]
PCIRSTN (output)
PCIRSTN (input)
PCISERRN
PCIMUINTN
1.
2.
3.
4.
5.
6.
IDT 79RC32438
This PCI interface conforms to the PCI Local Bus Specification, Rev 2.2.
PCICLK must be equal to or less than two times ICLK (PCICLK <= 2(ICLK)) with a maximum PCICLK of 66MHz.
The values for this symbol were determined by calculation, not by testing.
PCIRSTN is an output in host mode and an input in satellite mode.
To meet the PCI delay specification from reset asserted to outputs floating, the PCI reset should be logically combined with the COLDRSTN input, instead of input on PCIRSTN.
PCISERRN and PCIMUINTN use open collector I/O types.
1
Signal
2
6
6
4,5
4
Thigh_10a,
Symbol
Tslew_10a
Tpw_10d
Tpw_10e
Tper_10a
Tlow_10a
Tdz_10b
Tzd_10b
Tdz_10e
Thld_10b
Thld_10c
Tdo_10b
Tdo_10g
Tsu_10b
Tsu_10c
Tdo_10c
Thld_10f
Tdo_10f
Tsu_10f
3
3
3
3
3
Reference
none
PCICLK rising
PCICLK rising
None
None
PCIRSTN
falling
PCICLK rising
PCICLK rising
Edge
2(CLK)
6(CLK)
(CLK)
4000
15.0
200MHz
Min
6.0
3.0
2.0
2.0
5.0
3.0
4.7
1.5
2.0
2.0
—
0
0
0
Table 10 PCI AC Timing Characteristics
Max
14.0
30.0
11.1
4.0
6.0
6.0
6.0
—
—
—
—
—
—
—
—
—
—
—
2(CLK)
6(CLK)
(CLK)
4000
15.0
233MHz
Min
6.0
1.5
3.0
2.0
2.0
5.0
2.0
3.0
2.0
4.7
—
0
0
0
29 of 59
Max
30.0
14.0
11.1
4.0
6.0
6.0
6.0
—
—
—
—
—
—
—
—
—
—
—
2(CLK)
6(CLK)
(CLK)
4000
15.0
Min
266MHz
6.0
3.0
2.0
2.0
5.0
3.0
4.7
1.5
2.0
2.0
—
0
0
0
Max
30.0
14.0
11.1
4.0
6.0
6.0
6.0
—
—
—
—
—
—
—
—
—
—
—
2(CLK)
6(CLK)
(CLK)
4000
15.0
300MHz
Min
6.0
1.5
3.0
2.0
2.0
5.0
2.0
3.0
2.0
4.7
—
0
0
0
Max
30.0
14.0
11.1
4.0
6.0
6.0
6.0
—
—
—
—
—
—
—
—
—
—
—
Unit
V/ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
66 MHz PCI
Conditions
May 25, 2004
See Figure 13.
See Figure 13
(cont.)
See Figures 15
and 16
See Figure 13
Reference
Diagram
Timing