IDT79RC32K438-300BBG IDT, Integrated Device Technology Inc, IDT79RC32K438-300BBG Datasheet - Page 2

• Manufacturer Part Number: IDT79RC32K438-300BBG
• Description: IC MPU 32BIT CORE 300MHZ 416-BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: Interprise™r

Specifications of IDT79RC32K438-300BBG

• Processor Type: MIPS32 32-Bit
• Speed: 300MHz
• Voltage: 1.3V
• Mounting Type: Surface Mount
• Package / Case: 416-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Other names: 79RC32K438-300BBG

Device Overview
integrated communications processors. It incorporates a high perfor-
mance CPU core and a number of on-chip peripherals. The integrated
processor is designed to transfer information from I/O modules to main
IDT 79RC32438
The RC32438 is a member of the IDT™ Interprise™ family of PCI
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– 10 DMA channels: two channels for PCI (PCI to Memory and
– Provides flexible descriptor based operation
– Supports unaligned transfers (i.e., source or destination
– 10 and 100 Mb/s ISO/IEC 8802-3:1996 compliant
– Two IEEE 802.3u compatible Media Independent Interfaces
– MII supports IEEE 802.3u auto-negotiation speed selection
– Supports 64 entry hash table based multicast address filtering
– 512 byte transmit and receive FIFOs
– Supports flow control functions outlined in IEEE Std. 802.3x-
– Compatible with the 16550 and 16450 UARTs
– Two completely separate serial channels
– Modem control functions (CTS, RTS, DSR, DTR, RI, DCD)
– 16-byte transmit and receive buffers
– Programmable baud rate generator derived from the system
– Fully programmable serial characteristics:
– Line break generation and detection
– False start bit detection
– Internal loopback mode
– Supports standard 100 Kbps mode as well as 400 Kbps fast
– Supports 7-bit and 10-bit addressing
– Supports four modes: master transmitter, master receiver,
– Two 16550-compatible serial ports
– Interrupt controller
– System integrity functions
– General purpose I/O controller
– Serial peripheral interface (SPI)
– 4KB of high speed SRAM organized as 1K x 32 bits
– Supports burst and non-burst byte, halfword, triple-byte, and
– Rev. 2.6 compliant EJTAG Interface
DMA Controller
Two Ethernet Interfaces
Universal Asynchronous Receiver Transmitter (UART)
Additional General Purpose Peripherals
On-chip Memory
Debug Support
I
2
C-Bus
– 5, 6, 7, or 8 bit characters
– Even, odd or no parity bit generation and detection
– 1, 1-1/2 or 2 stop bit generation
Memory to PCI), two for each Ethernet interface, two channels
for memory to memory operations, two channels for external
operations
address may be on any byte boundary) with arbitrary byte
length.
(MII) with serial management interface
1997
clock
mode
slave transmitter, slave receiver
word CPU, PCI, and DMA accesses
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memory with minimal CPU intervention using a highly sophisticated
direct memory access (DMA) engine. All data transfers through the
RC32438 are achieved by writing data from an on-chip I/O peripheral to
main memory and then out to another I/O module.
CPU Execution Core
set architecture (ISA).
MIPS Technologies Inc. (www.mips.com). This core issues a single
instruction per cycle, includes a five stage pipeline, and is optimized for
applications that require integer arithmetic. The CPU core includes 16
KB instruction and 16 KB data caches. Both caches are 4-way set asso-
ciative and can be locked on a per line basis, which allows the
programmer control over this precious on-chip memory resource. The
core also features a memory management unit (MMU). The CPU core
also incorporates an enhanced joint test access group (EJTAG) inter-
face that is used to interface to in-circuit emulator tools, providing
access to internal registers and enabling the part to be controlled exter-
nally, simplifying the system debug process. The use of this core allows
IDT's customers to leverage the broad range of software and develop-
ment tools available for the MIPS architecture, including operating
systems, compilers, and in-circuit emulators.
Double Data Rate Memory Controller
(DDR) memory controller which supports both x16 and x32 memory
configurations up to 2GB. This module provides all of the signals
required to interface to both memory modules and discrete devices,
including two chip selects, differential clocking outputs and data strobes.
Memory and I/O Controller
a de-multiplexed 16-bit data and 26-bit address bus. It includes all of the
signals required to interface directly to as many as six Intel or Motorola-
style external peripherals, and the interface can be configured to
support both 8-bit and 16-bit peripherals.
DMA Controller
which operate in exactly the same manner. The DMA controller off-loads
the CPU core from moving data among the on-chip interfaces, external
peripherals, and memory. The controller supports scatter/gather DMA
with no alignment restrictions, appropriate for communications and
graphics systems.
PCI Interface
the PCI specification. An on-chip arbiter supports up to six external bus
masters, supporting both fixed priority and rotating priority arbitration
schemes. The part can support both satellite and host PCI configura-
tions, enabling the RC32438 to act as a slave controller for a PCI add-in
The 32-bit CPU core is 100% compatible with the MIPS32 instruction
Specifically, this device features the 4Kc CPU core developed by
The RC32438 incorporates a high performance double data rate
The RC32438 uses a dedicated local memory/IO controller including
The DMA controller consists of 10 independent DMA channels, all of
The PCI interface on the RC32438 is compatible with version 2.2 of
May 25, 2004