IDT79RC32K438-300BBG IDT, Integrated Device Technology Inc, IDT79RC32K438-300BBG Datasheet - Page 33

• Manufacturer Part Number: IDT79RC32K438-300BBG
• Description: IC MPU 32BIT CORE 300MHZ 416-BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: Interprise™r

Specifications of IDT79RC32K438-300BBG

• Processor Type: MIPS32 32-Bit
• Speed: 300MHz
• Voltage: 1.3V
• Mounting Type: Surface Mount
• Package / Case: 416-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Other names: 79RC32K438-300BBG

SPI
SCK
SDI
SDO
PCIEECS
SCK, SDI, SDO
1.
2.
3.
IDT 79RC32438
In SPI mode, the SCK period and sampling edge are programmable. In PCI mode, the SCK period is fixed and the sampling edge is rising.
PCIEECS is the PCI serial EEPROM chip select. It is an alternate function of PCIGNTN[1].
In Bit I/O mode, SCK, SDI, and SDO must meet the setup and hold times if they are synchronous or the minimum pulse width if they are asynchronous.
1
Signal
2
3
Thigh_15a,
Thigh_15a,
Thigh_15a,
Symbol
Tper_15a
Tper_15a
Tper_15a
Tlow_15a
Tlow_15a
Tlow_15a
Thld_15b
Tpw_15e
Tsu_15b
Tdo_15c
Tdo_15d
PCIEECS
SDO
SCK
SDI
Reference
None
SCK rising or
falling
SCK rising or
falling
SCK rising or
falling
None
Tdo_15d
Edge
Tper_15a
Figure 18 SPI AC Timing Waveform — PCI Configurations Load
Min
2(ICLK)
MSB
MSB
100 166667 100 166667 100 166667 100 166667
930
465
200MHz
40
60
60
Loading PCI configuration registers through SPI from an EEPROM.
—
—
0
0
Max
Table 13 SPI AC Timing Characteristics
83353
Tdo_15c
1920
960
990
495
60
60
bit 6
—
—
—
bit 6
Min
2(ICLK)
930
465
233MHz
40
60
60
—
—
0
0
bit 5
bit 5
33 of 59
Tsu_15b
Max
83353
1920
960
990
495
—
—
60
60
—
Thigh_15a
Thigh_15a
bit 4
bit 4
Min
2(ICLK)
930
465
266MHz
40
60
60
—
—
0
0
bit 3
bit 3
Max
83353
Tlow_15a
Tlow_15a
1920
960
990
495
60
60
—
—
—
Thld_15b
Min
2(ICLK)
bit 2
bit 2
930
465
300MHz
40
60
60
—
—
0
0
Max
83353
1920
bit 1
bit 1
960
990
495
60
60
—
—
—
Unit
LSB
LSB
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
33 MHz PCI
66 MHz PCI
SPI
33 MHz PCI
66 MHz PCI
SPI
SPI or PCI
SPI or PCI
PCI
Bit I/O
Conditions
May 25, 2004
See Figures 18,
19, 20 and 21.
Reference
Diagram
Timing