MPC850DSLZQ50BU Freescale Semiconductor, MPC850DSLZQ50BU Datasheet - Page 56

• Manufacturer Part Number: MPC850DSLZQ50BU
• Description: IC MPU PWRQUICC 50MHZ 256-PBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC850DSLZQ50BU

• Processor Type: MPC8xx PowerQUICC 32-Bit
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 256-PBGA
• Family Name: MPC8xx
• Device Core: PowerQUICC
• Device Core Size: 32b
• Frequency (max): 50MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Operating Temp Range: 0C to 95C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 256
• Package Type: BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant

CPM Electrical Characteristics
8.8
Figure 21
56
TENA(RTSx)
RENA(CDx)
SMC Transparent AC Electrical Specifications
MPC850 PowerQUICC™ Integrated Communications Processor Hardware Specifications, Rev. 2
provides the SMC transparent timings as shown in
(NOTE 2)
(Output)
TCLKx
(Input)
(Input)
TxDx
1
Num
151a
150
151
152
153
154
155
The ratio SyncCLK/SMCLKx must be greater or equal to 2/1.
NOTES:
1.
2.
128
SMCLKx clock period
SMCLKx width low
SMCLKx width high
SMCLKx rise/fall time
SMTXDx active delay (from SMCLKx falling edge)
SMRXDx/SMSYNx setup time
SMRXDx/SMSYNx hold time
Transmit clock invert (TCI) bit in GSMR is set.
If RENA is deasserted before TENA, or RENA is not asserted at all during transmit, then the
CSL bit is set in the buffer descriptor at the end of the frame transmission.
133
131
Table 21. Serial Management Controller Timing
Figure 55. Ethernet Transmit Timing Diagram
Characteristic
1
128
130
Figure
132
All Frequencies
129
56.
100.00
50.00
50.00
10.00
20.00
5.00
Min
—
15.00
50.00
Max
—
—
—
—
—
Freescale Semiconductor
Unit
134
ns
ns
ns
ns
ns
ns
ns