MC68EC020AA25 Freescale Semiconductor, MC68EC020AA25 Datasheet - Page 185

• Manufacturer Part Number: MC68EC020AA25
• Description: IC MPU 32BIT 25MHZ 100-QFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC020AA25

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 100-QFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 100
• Package Type: PQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

7.4.4 Null Primitive
The null coprocessor response primitive communicates coprocessor status information to
the main processor. This primitive applies to instructions in the general and conditional
categories. Figure 7-24 shows the format of the null primitive.
The null primitive uses the CA and PC bits as described in 7.4.2 Coprocessor Response
Primitive General Format.
The IA bit specifies the interrupts allowed optional operation. This bit determines whether
the MC68020/EC020 services pending interrupts prior to rereading the response CIR after
receiving a null primitive. Interrupts are allowed when the IA bit is set.
The PF bit shows the processing-finished status of the coprocessor. That is, PF = 1
indicates that the coprocessor has completed all processing associated with an
instruction.
The TF bit indicates the true/false condition during execution of a conditional category
instruction. TF = 1 is the true condition specifier; TF = 0 is the false condition specifier.
The TF bit is only relevant for null primitives with CA = 0 that are used by the coprocessor
during the execution of a conditional instruction.
The MC68020/EC020 processes a null primitive with CA = 1 in the same manner whether
executing a general or conditional category coprocessor instruction. If the coprocessor
sets CA and IA in the null primitive, the main processor services pending interrupts using
a midinstruction stack frame (refer to Figure 7-43) and reads the response CIR again. If
the coprocessor sets CA and clears IA in the null primitive, the main processor reads the
response CIR again without servicing any pending interrupts.
A null primitive with CA = 0 provides a condition evaluation indicator to the main processor
during the execution of a conditional instruction and ends the dialogue between the main
processor and coprocessor for that instruction. The main processor completes the
execution of a conditional category coprocessor instruction when it receives the primitive.
The PF bit is not relevant during conditional instruction execution since the primitive itself
implies completion of processing.
Usually, when the main processor reads any primitive that does not have CA = 1 while
executing a general category instruction, it terminates the dialogue between the main
processor and coprocessor. If a trace exception is pending, however, the main processor
does not terminate the instruction dialogue until it reads a null primitive with CA = 0 and
PF = 1 from the response CIR (refer to 7.5.2.5 Trace Exceptions). Thus, the main
processor continues to read the response CIR until it receives a null primitive with CA = 0
7-32
CA
15
PC
14
13
0
12
0
Figure 7-24. Null Primitive Format
11
1
10
0
M68020 USER’S MANUAL
9
0
IA
8
7
0
6
0
5
0
4
0
3
0
2
0
PF
1
TF
MOTOROLA
0