MPC8347CVRADDB Freescale Semiconductor, MPC8347CVRADDB Datasheet - Page 32

IC MPU PWRQUICC II 620-PBGA

MPC8347CVRADDB

Manufacturer Part Number
MPC8347CVRADDB
Description
IC MPU PWRQUICC II 620-PBGA
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MPC8347CVRADDB

Processor Type
MPC83xx PowerQUICC II Pro 32-Bit
Speed
266MHz
Voltage
1.2V
Mounting Type
Surface Mount
Package / Case
620-PBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-

Available stocks

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Part Number
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Quantity
Price
Part Number:
MPC8347CVRADDB
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
8.3.2
Table 30
Figure 16
32
At recommended operating conditions with LV
MDC frequency
MDC period
MDC clock pulse width high
MDC to MDIO delay
MDIO to MDC setup time
MDIO to MDC hold time
MDC rise time
MDC fall time
Notes:
1. The symbols for timing specifications follow the pattern of t
2. This parameter is dependent on the csb_clk speed (that is, for a csb_clk of 267 MHz, the maximum frequency is 8.3 MHz
3. This parameter is dependent on the csb_clk speed (that is, for a csb_clk of 267 MHz, the delay is 70 ns and for a csb_clk of
and t
timing (MD) for the time t
t
relative to the t
is used with the appropriate letter: R (rise) or F (fall).
and the minimum frequency is 1.2 MHz; for a csb_clk of 375 MHz, the maximum frequency is 11.7 MHz and the minimum
frequency is 1.7 MHz).
333 MHz, the delay is 58 ns).
MDDVKH
(first two letters of functional block)(reference)(state)(signal)(state)
provides the MII management AC timing specifications.
symbolizes management data timing (MD) with respect to the time data input signals (D) reach the valid state (V)
Parameter/Condition
shows the MII management AC timing diagram.
MPC8347E PowerQUICC™ II Pro Integrated Host Processor Hardware Specifications, Rev. 11
MII Management AC Electrical Specifications
MDC
(Output)
(Input)
MDIO
MDIO
clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention
MDC
MDC
Figure 16. MII Management Interface Timing Diagram
Table 30. MII Management AC Timing Specifications
from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time. Also,
t
MDCH
DD
t
is 3.3 V ± 10% or 2.5 V ± 5%.
MDDVKH
t
MDC
t
MDKHDX
Symbol
t
t
t
MDKHDX
MDDVKH
MDDXKH
t
t
t
f
t
MDCH
MDCR
MDHF
MDC
MDC
1
for outputs. For example, t
(first two letters of functional block)(signal)(state)(reference)(state)
t
MDCF
Min
32
10
5
0
t
MDDXKH
t
MDCR
Typ
400
2.5
MDKHDX
Max
symbolizes management data
170
10
10
Freescale Semiconductor
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
for inputs
Notes
2
3

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