MC68030FE16C Freescale Semiconductor, MC68030FE16C Datasheet - Page 176
MC68030FE16C
Manufacturer Part Number
MC68030FE16C
Description
IC MPU 32BIT ENHANCED 132-CQFP
Manufacturer
Freescale Semiconductor
Datasheet
1.MC68030FE20C.pdf
(599 pages)
Specifications of MC68030FE16C
Processor Type
M680x0 32-Bit
Speed
166MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
132-CQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
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Quantity
Price
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Part Number:
MC68030FE16C
Manufacturer:
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MOTOROLA
transferred. The slave device latches the byte and acknowledges the data
transfer, indicating that the port is 16 bits wide. When the processor starts
the second cycle, the size signals specify that three bytes remain to be trans-
data items should be aligned on their natural boundaries. All instruction
words and extension words must reside on word boundaries. Attempting to
exception.
word-organized memory, which requires three bus cycles. For the first cycle,
the size signals specify a long-word transfer, and the address offset (A2:A0)
ferred with an address offset (A2:A0) of 010. The next two bytes are trans-
ferred during this cycle. The processor then initiates the third cycle, with the
size signals indicating one byte remaining to be transferred. The address
offset (A2:A0) is now 100; the port latches the final byte; and the operation
organized memory. This example is similar to the one shown in Figures 7-9
and 7-10 except that the operand is word sized and the transfer requires only
two bus cycles.
long-word or word operands that are misaligned. For maximum performance,
prefetch an instruction word at an odd address causes an address error
Figure 7-9 shows the transfer of a long-word operand to an odd address in
is 001. Since the port width is 16 bits, only the first byte of the long word is
is complete. Figure 7-10 shows the associated bus transfer signal timing.
Figure 7-1 1 shows the equivalent operation for a cachable data read cycle.
Figures 7-12 and 7-13 show a word transfer to an odd address in word-
Figure 7-14 shows the equivalent operation for a cachable data read cycle.
Figure 7-9. Misaligned Long-Word Transfer to Word Port Example
I
031
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31
oP0 I
XXX
OPI
OP3
MSB
WORD MEMORY
DATA BUS
OPO
OP2
XXX
LSB
LONG WORD OPERAND
oP,
MC68030 USER'S MANUAL
Dlfi
I
I
oP2 I
SIZI
0
0
I
SIZO
0
i
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MCSO030
A2
l
0
0
A1
0
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AO
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0
1
0
DSACKi
MEMORY CONTROL
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DSACKO
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7-15
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