MPC8245LZU333D Freescale Semiconductor, MPC8245LZU333D Datasheet - Page 48

• Manufacturer Part Number: MPC8245LZU333D
• Description: IC MPU 32BIT 333MHZ 352-TBGA
• Manufacturer: Freescale Semiconductor
• Series: PowerQUICC IIr

Specifications of MPC8245LZU333D

• Processor Type: MPC82xx PowerQUICC II 32-bit
• Speed: 333MHz
• Voltage: 2V
• Mounting Type: Surface Mount
• Package / Case: 352-TBGA
• Core Size: 32 Bit
• Program Memory Size: 32KB
• Cpu Speed: 333MHz
• Embedded Interface Type: I2C
• Digital Ic Case Style: TBGA
• No. Of Pins: 352
• Supply Voltage Range: 1.9V To 2.2V
• Rohs Compliant: No
• Family Name: MPC82XX
• Device Core: PowerPC
• Device Core Size: 64b
• Frequency (max): 333MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 2/2.1/3.3V
• Operating Supply Voltage (max): 2.2/3.465V
• Operating Supply Voltage (min): 1.9/3.135V
• Operating Temp Range: 0C to 105C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 352
• Package Type: TBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant

System Design
reset sources, such as voltage monitors, watchdog timers, power supply failures, or push-button switches,
the COP reset signals must be merged into these signals with logic.
The arrangement shown in
Figure 26
allows the COP port to independently assert HRESET or TRST,
while ensuring that the target can drive HRESET as well. If the JTAG interface and COP header will not
be used, TRST should be tied to HRESET through a 0-Ω isolation resistor so that it is asserted when the
system reset signal (HRESET) is asserted, ensuring that the JTAG scan chain is initialized during
power-on. Although Freescale recommends that the COP header be designed into the system as shown in
Figure
26, if this is not possible, the isolation resistor will allow future access to TRST in the case where
a JTAG interface may need to be wired onto the system in debug situations.
The COP interface has a standard header for connection to the target system based on the 0.025"
square-post, 0.100" centered header assembly (often called a Berg header). Typically, pin 14 is removed
as a connector key.
There is no standardized way to number the COP header shown in
Figure
26. Consequently, different
emulator vendors number the pins differently. Some pins are numbered top-to-bottom and left-to-right
while others use left-to-right then top-to-bottom and still others number the pins counter clockwise from
pin 1 (as with an IC). Regardless of the numbering, the signal placement recommended in
Figure 26
is
common to all known emulators.
MPC8245 Integrated Processor Hardware Specifications, Rev. 10
48
Freescale Semiconductor