MC68030FE25C Freescale Semiconductor, MC68030FE25C Datasheet - Page 25

• Manufacturer Part Number: MC68030FE25C
• Description: IC MPU 32BIT ENHANCED 132-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68030FE25C

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 25MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 132
• Package Type: CQUAD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

AC ELECTRICAL SPECIFICATIONS — READ AND WRITE CYCLES
M O T O R O L A
25A
Nu m.
28A
29A
30A
(Continued)
15A
31A
37A
25
26
28
29
30
27A
39A
31
16
17
18
20
21
22
23
24
27
32
33
34
35
37
39
40
41
42
43
11
9,11
11
12
12
12
2
12
12
12
8
3
6
DS
Clock High to
AS
Clock High to R/
Clock High to R/
R/
R/
Clock High to Data-Out Valid
Data-Out Valid to Negating Edge of
AS
DS
Data-Out Valid to
Data-In Valid to Clock Low (Setup)
Late
AS, DS Negated to
(Asynchronous Hold)
Clock Low to
(Synchronous Hold)
AS
AS
Clock Low to Data-In Invalid (Synchronous Hold)
Clock Low to Data-In High Impedance (Read followed by Write)
DSACKx
DSACKx
RESET
Clock Low to
Clock Low to
BR
BGACK
BGACK
BG
BG
Clock High to
Clock Low to
Clock Low to
Clock High to
W
W
,
,
,
,
Negated to
Negated to
Asserted to
Width Negated
DS
DS
DS
DS
Width Asserted
BERR/HALT
High to
Low to
Input Transition Time
Negated to R/
Negated to Data-Out Invalid
Negated to Data-In Invalid (Asynchronous Hold)
Negated to Data-In High Impedance
Asserted to
Asserted to
Asserted to Data-In Valid (Asynchronous Data Setup)
Asserted to
AS
DS
BG
DBEN
BG
DBEN
DSACKx
AS
DBEN
DBEN
DBEN
AS
BG
W
W
Asserted
Asserted (Write)
,
Negated
Asserted
DS
DS
High
Low
Asserted
Asserted to Clock Low (Setup)
DSACKx
Asserted (
Negated (Read)
Asserted (Write)
BG
BR
Negated (Write)
, R/
Asserted (Read)
Asserted (Write)
W
Negated (Write)
Freescale Semiconductor, Inc.
,
DSACKx
Characterstics
BERR
W
Negated
Negated
Invalid
For More Information On This Product,
,
MC68EC030 TECHNICAL DATA
DBEN
,
RMC
BERR
,
HALT
Valid (Skew)
,
Go to: www.freescale.com
AS
CBREQ
Not Asserted)
,
HALT
,
AVEC
,
High Impedance
AVEC
Negated
Negated
Min
1.5
1.5
25
47
60
60
—
2 5 M H z
—
—
—
—
—
—
7
0
0
7
5
7
7
7
5
0
8
0
8
0
0
0
0
0
0
0
2
M a x
1.5
3.5
3.5
1.5
—
—
—
60
—
20
20
—
40
—
20
20
—
—
20
—
—
—
—
40
70
40
—
28
20
20
—
20
20
7
Min
1.5
1.5
40 MHz
16
—
24
—
—
—
—
—
30
30
—
3
0
0
5
3
3
3
3
3
0
6
0
6
0
0
0
0
0
0
1
0
M a x
1.5
3.5
3.5
1.5
—
—
—
30
—
16
16
—
25
—
14
14
—
—
14
—
—
—
—
20
40
25
—
14
14
14
—
16
16
3
Unit
Clks
Clks
Clks
Clks
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2 5