MC68EC040FE20A Freescale Semiconductor, MC68EC040FE20A Datasheet - Page 144

• Manufacturer Part Number: MC68EC040FE20A
• Description: IC MPU 32BIT 20MHZ 184-CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68EC040FE20A

• Processor Type: M680x0 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 184-CQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

negate logic levels. The exceptions to this rule are the TIP, TA, and B B signals that
transition between logic levels during T4 but transition from a driven state to a high-
impedance state during T1. The input setup time (t
time (t
timing specifications in Section 11 MC68040 Electrical and Thermal Characteristics.
Inputs to the M68040 (other than the IPL2–IPL0 and RSTI signals) are synchronously
sampled and must be stable during the sample window defined by t
Figure 7-1) to guarantee proper operation. The asynchronous IPL≈ and RSTI signals are
also sampled on the rising edge of BCLK, but are internally synchronized to resolve the
input to a valid level before using it. Since the timing specifications for the M68040 are
referenced to the rising edge of BCLK, they are valid only for the specified operating
frequency and must be scaled for lower operating frequencies.
7-2
ho
), and delay time (t
NOTES:
PHASE-LOCKED
INTERNALLY
1.
2.
3.
4.
5.
6.
OUTPUTS
t d
t ho
t ho' = Output hold time relative to BCLK rising edge;
t su
t hi
t d'
INPUTS
Figure 7-1. Signal Relationships to Clocks
PCLK
BCLK
= Propagation delay of signal relative to BLK rising edge.
= Propagation delay of signal relative to PCLK falling edge.
= Output hold time relative to BCLK rising edge.
= Required input setup time relative to BCLK rising edge.
= Required input hold time relative to BCLK rising edge.
except for TIP, TA, BB when used as outputs.
Freescale Semiconductor, Inc.
For More Information On This Product,
d
) illustrated in Figure 7-1 are described in the AC electrical
M68040 USER’S MANUAL
Go to: www.freescale.com
T1
T2
t su
su
t hi
T3
t ho
), input hold time (t
t ho' t h
t d
=
t ho'
–1/2 PCLK.
T4
;
t d'
t d' t d
=
–1/2 PCLK
T1
su
, t
hi
hi
, and t
), output hold
MOTOROLA
ho
(see