MPC8533EVTANG Freescale Semiconductor, MPC8533EVTANG Datasheet - Page 9

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MPC8533EVTANG

Manufacturer Part Number
MPC8533EVTANG
Description
MPU POWERQUICC 783-PBGA
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MPC8533EVTANG

Processor Type
MPC85xx PowerQUICC III 32-Bit
Speed
800MHz
Voltage
1V
Mounting Type
Surface Mount
Package / Case
783-FCPBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-

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2.4.2
The e500 coherency module (ECM) provides a mechanism for I/O-initiated transactions to snoop the bus
between the e500 core and the integrated L2 cache in order to maintain coherency across local cacheable
memory. It also provides a flexible switch-type structure for core- and I/O-initiated transactions to be
routed or dispatched to target modules on the device.
The MPC8533E supports a flexible 36-bit physical address map. Conceptually, the address map consists
of local space and external address space. The local address map is supported by ten local access windows
that define mapping within the local 36-bit (64-Gbyte) address space.
The MPC8533E can be made part of a larger system address space through the mapping of translation
windows. This functionality is included in the address translation and mapping units (ATMUs). Both
inbound and outbound translation windows are provided. The ATMUs allows the MPC8533E to be part of
larger address maps such as the PCI or PCI Express 64-bit address environment.
2.4.3
The SEC is a modular and scalable security core optimized to process all the algorithms associated with
IPSec, IKE, WTLS/WAP, SSL/TLS, and 3GPP. Although it is not a protocol processor, the SEC is
designed to perform multi-algorithmic operations (for example, 3DES-HMAC-SHA-1) in a single pass of
the data. The version of the SEC used in the MPC8533E is specifically capable of performing single-pass
security cryptographic processing for SSL 3.0, SSL 3.1/TLS 1.0, IPSec, SRTP, and 802.11i.
2.4.4
Two on-chip enhanced three-speed Ethernet controllers (eTSECs) incorporate a media access control
(MAC) sublayer that supports 10 and 100 Mbps and 1 Gbps Ethernet/802.3 networks with MII, RMII,
Freescale Semiconductor
Compatible with code written for the Freescale MPC8548E, MPC8541E and MPC8555E devices
XOR engine for parity checking in RAID storage applications.
Four crypto-channels, each supporting multi-command descriptor chains
Cryptographic execution units:
— PKEU—public key execution unit
— DEU—Data Encryption Standard execution unit
— AESU—Advanced Encryption Standard unit
— AFEU—ARC four execution unit
— MDEU—message digest execution unit
— KEU—Kasumi execution unit
— RNG—Random number generator
e500 Coherency Module (ECM) and Address Map
Integrated Security Engine (SEC)
Enhanced Three-Speed Ethernet Controllers (eTSEC)
The features described in this section are available only on the MPC8533E.
The MPC8533 does not contain an integrated security engine.
MPC8533E Integrated Host Processor Product Brief, Rev. 0
NOTE
Features
9

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