MC68030RC25C Freescale Semiconductor, MC68030RC25C Datasheet - Page 106

• Manufacturer Part Number: MC68030RC25C
• Description: IC MPU 32BIT ENHANCED 128-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68030RC25C

• Processor Type: M680x0 32-Bit
• Speed: 25MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 128-PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

MOTOROLA
cpRESTORE If supervisor state
cpTRAPcc
cpSAVE
Opcode
cpDBcc
cpGEN
CMPM
CMPA
CMP2
cpBcc
cpScc
DIVSL
DIVUL
CAS2
CHK2
CMPI
DIVU
CMP
DBcc
DIVS
EORI
CAS
CHK
EOR
CLR
CAS Destination - - Compare Operand i) cc;
CAS2 Destination 1 - - Compare 1 i cc;
0 i Destination
Destination - - Source
Destination - - Immediate Data
Compare Rn < lower-bound or
If cpcc true then scanPC + d I) PC
else TRAP
If supervisor state
else TRAP
else 0s I Destination
Source O Destination i. Destination
If Dn < 0 or Dn > Source then TRAP
If Rn < lower bound or
Destination - - Source ~ cc
Destination - - Source ~ cc
If cpcc false then (Dn
If cpcc true then ls I Destination
If cpcc true then TRAP
If condition false then (Dn - 1 J) Dn;
If Dn#- -1 then PC+d I PC)
Destination/Source J Destination
Destination/Source ~ Destination
Immediate Data (~ Destination j Destination
Pass Command Word to Coprocessor
then TRAP
else Destination 1 j Compare 1; Destination 2 o Ccmpare 2
Rn > upper bound
and Set Condition Codes
then Restore Internal State of Coprocessor
then Save Internal State of Coprocessor
if Z, Update Operand I) Destination
else Destination 0 Compare Operand
if Z, Destination 2 - - Compare I) cc;
if Z, Update 1 0 Destination 1; Update 2 i) Dest r:e::c" 2
Rn > upper-bound
If Dn =~ - 1 then ecanPC+d j PC)
Table 3-14. Instruction Set Summary (Sheet 2 of 5)
1 0 Dn;
Operation
MC68030 USER'S MANUAL
CAS Dc,Du,(ea)
CAS2 Dcl :Dc2,Dul :Du2,(Rn 1 ):(Rn2)
CHK (ea),Dn
CHK2 (ea),Rn
cpTRAPcc #(data)
DIVU.L (ea),Dr:Dq
DIVUL.L (ea),Dr:Dq 32/32 j 32r:32,q
EOR Dn,(ea)
EORI #(data),(ea)
CLR (ea)
CMP (ea),Dn
CMPA (ea),An
CMPI #(data),(ea)
CMPM (Ay)+ ,(Ax)+
CMP2 (ea),Rn
cpBcc (label)
cpDBcc Dn,(labe0
cpGEN (parameters as defined by co-
processor)
cpRESTORE (ea)
cpSAVE (ea)
cpScc (ea)
cpTRAPcc
DBcc Dn,(label)
DIVS.W (ea),Dn
DIVS.L (ea),Dq
DIVS.L (ea),Dr:Dq
DIVSL.L (ea),Dr:Dq 32/32 i 32r:32q
DIVU.W (ea),Dn
DIVU.L (ea),Dq
Syntax
32/32 1 32q
64/32 I 32r:32q
32/32 0 32q
64/32 0 32r:32q
32/16 I) 16r:i6q
32/16 i 16r.16q
3-21