MC68020FE33E Freescale Semiconductor, MC68020FE33E Datasheet - Page 223

• Manufacturer Part Number: MC68020FE33E
• Description: IC MICROPROCESSOR 32BIT 132CQFP
• Manufacturer: Freescale Semiconductor

Specifications of MC68020FE33E

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 132-CQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -

8.2 INSTRUCTION TIMING TABLES
The instruction times given in the following illustration include the following assumptions
about the MC68020/EC020 system:
There are three values given for each instruction and addressing mode:
The only instances for which the size of the operand has any effect are the instructions
with immediate operands. Unless specified otherwise, immediate byte and word operands
have identical execution times.
Within each set or column of instruction timings are four sets of numbers, three of which
are enclosed in parentheses. The bolded outer number is the total number of clocks for
the instruction. The first number inside the parentheses is the number of operand read
cycles performed by the instruction. The second value inside parentheses is the number
of instruction accesses performed by the instruction, including all prefetches to keep the
instruction pipe filled. The third value within parentheses is the number of write cycles
performed by the instruction. One example from the instruction timing table is:
The total number of bus-activity clocks for the previous example is derived in the following
way:
The example used here was taken from a worst-case fetch effective address time. The
addressing mode was ([d
MOTOROLA
1. All operands are long-word aligned as is the stack,
2. The data bus is 32 bits, and
3. Memory access occurs with no wait states (three-cycle read/write).
1. The best case (BC), which reflects the time (in clocks) when the instruction is in the
2. The cache-only case (CC) when the instruction is in the cache but has no overlap,
3. The worst case (WC) when the instruction is not in the cache or the cache is
cache and benefits from maximum overlap due to other instructions,
and
disabled and there is no instruction overlap.
(2 Reads * 3 Clocks/Read) + (3 Instruction Accesses * 3 Clocks/Access)
24 Total Clocks – 15 Clocks (Bus Activity) = 9 Internal Clocks
+ (0 Writes * 3 Clocks/Write) = 15 Clocks of Bus Activity
Freescale Semiconductor, Inc.
NUMBER OF INSTRUCTION ACCESS CYCLES
For More Information On This Product,
32
,B],I,d
Go to: www.freescale.com
M68020 USER’S MANUAL
TOTAL NUMBER OF CLOCKS
NUMBER OF WRITE CYCLES
NUMBER OF READ CYCLES
32
). The same addressing mode under the best-case
24
(2
/
3
/
0)
8- 9