MC68LC040RC40A Freescale Semiconductor, MC68LC040RC40A Datasheet - Page 212
MC68LC040RC40A
Manufacturer Part Number
MC68LC040RC40A
Description
IC MPU 32BIT 40MHZ 179-PGA
Manufacturer
Freescale Semiconductor
Datasheet
1.MC68EC040FE33A.pdf
(442 pages)
Specifications of MC68LC040RC40A
Processor Type
M680x0 32-Bit
Speed
40MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
179-PGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
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transfer. Edge-triggered latch B is clocked by the rising edge of BCLK and latches the
data from latch A for use by internal logic.
Figure 7-48 illustrates the data read timing for both normal operation and DLE mode.
During normal operation (i.e., DLE mode disabled), latch A is always transparent, and by
the rising edge of BCLK, read data is latched. Data must meet setup and hold time
specifications #15 and #16 in this case. When the DLE mode is enabled, the data can be
latched by the rising edge of BCLK or the falling edge of DLE, depending on the timing for
DLE.
7-70
TA, TEA, TBI
EXTERNAL
DATA BUS
DLE
Figure 7-47. DLE Mode Block Diagram
Freescale Semiconductor, Inc.
For More Information On This Product,
M68040 USER’S MANUAL
TRANSPARENT
Go to: www.freescale.com
LATCH - A
D
G
Q
EDGE-TRIGGERED
LATCH - B
D
BCLK
Q
WRITE DATA
TERMINATION
CONTROL
LATCHED
READ DATA
MOTOROLA
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