MPC8560PX833LC Freescale Semiconductor, MPC8560PX833LC Datasheet - Page 2

• Manufacturer Part Number: MPC8560PX833LC
• Description: IC MPU PWRQUICC III 783-FCPBGA
• Manufacturer: Freescale Semiconductor

Specifications of MPC8560PX833LC

• Processor Type: MPC85xx PowerQUICC III 32-Bit
• Speed: 833MHz
• Voltage: 1.2V
• Mounting Type: Surface Mount
• Package / Case: 783-FCPBGA
• Family Name: MPC85XX
• Device Core: PowerQUICC III
• Device Core Size: 32b
• Frequency (max): 833MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 1.2V
• Operating Supply Voltage (max): 1.26V
• Operating Supply Voltage (min): 1.14V
• Operating Temp Range: 0C to 105C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 783
• Package Type: FCBGA
• For Use With: MPC8560ADS-BGA - BOARD APPLICATION DEV 8560
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Not Compliant

Overview
1
The following section provides a high-level overview of the device features.
functional units within the MPC8560.
1.1
The following lists an overview of the MPC8560 feature set:
2
RMIIs
MIIs,
•
•
UTOPIAs
Overview
High-performance, 32-bit Book E–enhanced core that implements the Power Architecture
— 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache with parity protection. Caches can
— Memory management unit (MMU) especially designed for embedded applications
— Enhanced hardware and software debug support
— Performance monitor facility (similar to but different from the device performance monitor
High-performance RISC CPM operating at up to 333 MHz
— CPM software compatibility with previous PowerQUICC families
— One instruction per clock
TDMs
MPHY
SDRAM
I/Os
Key Features
GPIO
IRQs
be locked entirely or on a per-line basis. Separate locking for instructions and data
described in Chapter 18, “Performance Monitor.”
DDR
32b
DDR SDRAM Controller
Local Bus Controller
Interrupt Controller
Programmable
MPC8560 Integrated Processor Hardware Specifications, Rev. 5
I
2
C Controller
CPM
MCC
MCC
SCC
SCC
SCC
SCC
FCC
FCC
FCC
SPI
I2C
Parallel I/O
Generators
Baud Rate
Controller
I-Memory
Interrupt
DPRAM
Engine
Timers
Serial
CPM
ROM
RISC
DMA
Figure 1. MPC8560 Block Diagram
Coherency
Module
OCeaN
e500
256-Kbyte
L2-Cache/
SRAM
RapidIO Controller
10/100/1000 MAC
10/100/1000 MAC
DMA Controller
PCI Controller
Figure 1
32-Kbyte L1
I Cache
Core Complex Bus
e500 Core
Freescale Semiconductor
shows the major
MII, GMII, TBI,
RTBI, RGMIIs
32-Kbyte L1
D Cache
RapidIO-8
16 Gb/s
PCI 64b
133 MHz