MC68020RC33E Freescale Semiconductor, MC68020RC33E Datasheet - Page 4

• Manufacturer Part Number: MC68020RC33E
• Description: IC MICROPROCESSOR 32BIT 114-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68020RC33E

• Processor Type: M680x0 32-Bit
• Speed: 33MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 114-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 33.33MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 114
• Package Type: PGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

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Paragraph
3.12
3.13
4.1
4.2
4.3
4.3.1
4.3.2
5.1
5.1.1
5.1.2
5.1.3
5.1.4
5.1.5
5.1.6
5.1.7
5.2
5.2.1
5.2.2
5.2.3
5.2.4
5.2.5
5.2.6
5.2.7
5.3
5.3.1
5.3.2
5.3.3
5.4
5.4.1
5.4.1.1
5.4.1.2
5.4.1.3
5.4.2
5.4.3
5.5
5.5.1
viii
Number
Power Supply Connections ..................................................................... 3-7
Signal Summary...................................................................................... 3-8
On-Chip Cache Organization and Operation .......................................... 4-1
Cache Reset ........................................................................................... 4-3
Cache Control ......................................................................................... 4-3
Bus Transfer Signals............................................................................... 5-1
Data Transfer Mechanism....................................................................... 5-5
Data Transfer Cycles .............................................................................. 5-25
CPU Space Cycles ................................................................................. 5-44
Bus Exception Control Cycles................................................................. 5-53
Cache Control Register (CACR) ......................................................... 4-3
Cache Address Register (CAAR) ........................................................ 4-4
Bus Control Signals ............................................................................. 5-2
Address Bus ........................................................................................ 5-3
Data Strobe ......................................................................................... 5-4
Data Buffer Enable .............................................................................. 5-4
Bus Cycle Termination Signals............................................................ 5-4
Dynamic Bus Sizing ............................................................................ 5-5
Misaligned Operands........................................................................... 5-14
Effects of Dynamic Bus Sizing and Operand Misalignment ................ 5-20
Address, Size, and Data Bus Relationships ........................................ 5-21
Cache Interactions .............................................................................. 5-22
Synchronous Operation with DSACK1/DSACK0 ............................... 5-24
Read Cycle .......................................................................................... 5-26
Write Cycle .......................................................................................... 5-33
Read-Modify-Write Cycle..................................................................... 5-39
Interrupt Acknowledge Bus Cycles ...................................................... 5-45
Breakpoint Acknowledge Cycle ........................................................... 5-50
Coprocessor Communication Cycles .................................................. 5-53
Address Strobe .................................................................................... 5-3
Data Bus.............................................................................................. 5-3
Bus Operation ..................................................................................... 5-24
Bus Errors ........................................................................................... 5-55
TABLE OF CONTENTS (Continued)
Interrupt Acknowledge Cycle—Terminated Normally ...................... 5-45
Autovector Interrupt Acknowledge Cycle ......................................... 5-48
Spurious Interrupt Cycle .................................................................. 5-48
Freescale Semiconductor, Inc.
For More Information On This Product,
SECTION 1: OVERVIEW
On-Chip Cache Memory
M68020 USER’S MANUAL
Go to: www.freescale.com
Bus Operation
Section 4
Section 5
Title
UM Rev.1.0
MOTOROLA
Number
Page