MC68040RC40V Freescale Semiconductor, MC68040RC40V Datasheet - Page 177
MC68040RC40V
Manufacturer Part Number
MC68040RC40V
Description
IC MICROPROCESSOR 32BIT 179-PGA
Manufacturer
Freescale Semiconductor
Datasheet
1.MC68EC040FE33A.pdf
(442 pages)
Specifications of MC68040RC40V
Processor Type
M680x0 32-Bit
Speed
40MHz
Voltage
5V
Mounting Type
Surface Mount
Package / Case
179-PGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
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7.5.2 Breakpoint Interrupt Acknowledge Bus Cycle
The execution of a breakpoint instruction (BKPT) generates the breakpoint interrupt
acknowledge bus cycle. An acknowledged access is indicated with TT1 and TT0 = $3,
address A31–A0 = $00000000, and TM2–TM0 = $0. When the external device terminates
the cycle with either TA or TEA, the processor takes an illegal instruction exception.
Figures 7-24 and 7-25 illustrate a flowchart and functional timing diagram for a breakpoint
interrupt acknowledge transfer.
MOTOROLA
Figure 7-24. Breakpoint Interrupt Acknowledge Bus Cycle Flowchart
10) ASSERT TIP
1) SET R/W TO READ
2) DRIVE A31–A0 TO $00000000
3) DRIVE UPA1, UPA0 TO $0
4) SET SIZE TO BYTE
5) SET TRANSFER TYPE ON TT1, TT0 TO $3
6) SET TRANSFER MODIFIER TM2–TM0 TO $0
8) NEGATE CIOUT
9) ASSERT TS FOR ONE CLOCK
INSTRUCTION EXCEPTION PROCESSING
BREAKPOINT ACKNOWLEDGE
INITIATE ILLEGAL
PROCESSOR
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
M68040 USER’S MANUAL
1) NEGATE TA OR TEA
ASSERT TA OR TEA
EXTERNAL DEVICE
TERMINATE CYCLE
7- 35
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