MC8640DVU1000HE Freescale Semiconductor, MC8640DVU1000HE Datasheet
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MC8640DVU1000HE
Specifications of MC8640DVU1000HE
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MC8640DVU1000HE Summary of contents
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... Figure 1 shows the major functional units within the MPC8640 and MPC8640D. The major difference between the MPC8640 and MPC8640D is that there are two cores on the MPC8640D. © Freescale Semiconductor, Inc., 2009. All rights reserved. Document Number: MPC8640DEC Rev. 3, 07/2009 Contents 1. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2 ...
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... Switch Fabric PCI Express Four-Channel DMA Controller Figure 1. MPC8640 and MPC8640D e600 Core Block e600 Core 1-Mbyte L2 Cache 32-Kbyte L1 Data Cache Platform Interface or Interface [ x1/x2/x4/x8 PCI Exp (4 GB/s) AND 1x/4x SRIO (2.5 GB/ [2-x1/x2/x4/x8 PCI Express (8 GB/S) ] Interface External Control Freescale Semiconductor ...
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... Four outbound windows plus default translation for PCI Express interface unit — Eight outbound windows plus default translation for serial RapidIO® interface unit with segmentation and subsegmentation support MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Overview 3 ...
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... Programming model is compliant with the OpenPIC architecture — Supports 16 programmable interrupt and processor task priority levels — Supports 12 discrete external interrupts and 48 internal interrupts — Eight global high resolution timers/counters that can generate interrupts MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev Freescale Semiconductor ...
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... Programming model compatible with the original 16450 UART and the PC16550D • IEEE 1149.1™-compliant, JTAG boundary scan • Available as 1023 pin Hi-CTE flip chip ceramic ball grid array (FC-CBGA) MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 2 C addressing mode Overview 2 C interface ...
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... Value –0 –0 –0 –0 –0 –0.3 to 1.21V V –0.3 to 1.21V V –0.3 to 1.21V V –0 –0 –0 –0 –0 –0 –0.3 to 3.63V V Freescale Semiconductor 2 — — — — — — — — ...
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... Cores PLL supply SerDes Transceiver Supply (Ports 1 and 2) SerDes Serial I/O Supply Port 1 SerDes Serial I/O Supply Port 2 SerDes DLL and PLL supply voltage for Port 1 and Port 2 MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 1 (continued) Symbol ...
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... Figure shown in Figure 2 during regular run time shown in Figure 2 during regular run time. DD Figure 2 Specifications,” for details on the recommended _PLAT = 1.05 V devices. Refer to DD _Core Sequencing,” and not necessarily Freescale Semiconductor Notes — — — 5,6 — 12 Table 74 ...
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... LVCMOS type specifications. The DDR SDRAM interface uses a single-ended differential receiver referenced to each externally supplied Dn_MV to Dn_GV / appropriate for the (SSTL-18 and SSTL-25) electrical signaling standards. DD MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor + 20 GND GND – ...
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... MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev Table 3. Output Drive Capability Programmable Output Impedance (Ω (half strength mode (half strength mode 150 100 = 105C and _GV j Supply Notes Voltage D n _GV = 2 _GV = 1 3 T/ T/ 1.1/1. (min). DD Freescale Semiconductor ...
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... Beyond this, the power supplies may power down simultaneously if the preservation of DDRn memory is not a concern. See Figure 3 for more details on the power and reset sequencing details. MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor NOTE , and Dn_MV DD NOTE _PLAT, AV ...
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... Initialization,” for additional information on PLL relock and reset signal Section 5, “RESET reaches 10% of their recommended voltage. L/T/ 1.8/2 REF V _PLAT, AV _PLAT DD DD _SRDS n AV _LB _SRDS _Core _Core Relock Time Time Asserted for 5 e600 100 μs after PLL 4 6 Table 2. Initialization,” for more Freescale Semiconductor ...
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... Per Core PLL voltage supply Per Core voltage Supply Per Core PLL voltage supply Per Core voltage Supply Per Core PLL voltage supply DDR Controller I/O voltage supply MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor V _Coren, DD Platform V _PLAT ...
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... DD V _Coren, DD Platform V _PLAT DD Frequency (MHz) (Volts) 500 MHz 1.05 V 500 MHz 1. Power (Watts) 0.11 0.08 0.70 0.66 0.10 0.45 3.5 3.5 0.0125 Table 6. Junction Power Temperature (Watts 13.3 16.5 o 105 11.9 14.8 o 105 C 17 Freescale Semiconductor Notes — 5 — Notes ...
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... Table 8 provides the system clock (SYSCLK) AC timing specifications for the MPC8640. At recommended operating conditions (see Parameter SYSCLK frequency SYSCLK cycle time SYSCLK rise and fall time MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor V _Coren, DD Platform V _PLAT DD Frequency (MHz) ...
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... OV = 3.3 V ± 165 mV DD Symbol Min KHK SYSCLK — — Table 2. Min — — Table 8. . Typical Max Unit — — 150 ps and Section 18.3, “e600 to MPX clock PLL Table 8 considers Table 9 Max Unit 50 kHz 1.0 % Freescale Semiconductor Notes are Notes ...
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... The MPX platform clock frequency must be considered for proper operation of the high-speed PCI Express and Serial RapidIO interfaces as described below. For proper PCI Express operation, the MPX clock frequency must be greater than or equal to: MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor . There is no minimum RTC frequency; RTC may be MPX Symbol ...
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... MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev Min 100 3 100 4 2 — Table 12. PLL Lock Times Min Max — 100 — 50 Max Unit Notes μs — — — SYSCLKs 1 μs — 2 — SYSCLKs 1 — SYSCLKs 1 5 SYSCLKs 1 Unit Notes μs 1 μs — Freescale Semiconductor ...
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... Parameter Input/output capacitance: DQ, DQS, DQS Delta input/output capacitance: DQ, DQS, DQS Note: 1. This parameter is sampled _GV V = 0.2 V. OUT(peak-to-peak) MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor (typ) = 2.5 V and DDR2 SDRAM Symbol Min D n _GV 1.71 DD 0.49 × _GV ...
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... D n _MV + 0.04 V REF D n _GV + 0 _MV – 0.15 V REF μA 50 — mA — variations as measured at the receiver. . REF . DD (typ Min Max Unit — 0 _GVDD/2, OUT REF Min Max Unit μA — 500 Freescale Semiconductor Notes — — 4 — — Notes 1 1 Note 1 ...
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... MDQS[n]. This should be subtracted from the total timing budget. 2. The amount of skew that can be tolerated from MDQS to a corresponding MDQ signal is called t determined by the following equation: t absolute value CISKEW 3. Maximum DDR1 frequency is 400 MHz. MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Table 2) Symbol Min V — IL ...
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... MHz 1.95 t DDKHAX 533 MHz 1.48 400 MHz 1.95 t DDKHCS 533 MHz 1.48 400 MHz 1.95 t DDKHCX 533 MHz 1.48 400 MHz 1.95 t –0.6 DDKHMH t DISKEW Max Unit — — ns — — ns — — ns — — 0.6 ns Freescale Semiconductor Notes ...
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... Per the JEDEC spec the DDR2 duty cycle at 400 and 533 MHz is the low and high cycle time values. For the ADDR/CMD setup and hold specifications in assumed that the Clock Control register is set to adjust the memory clocks by 1/2 applied cycle. MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Table 2). 1 Symbol ...
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... Figure 6. DDR SDRAM Output Timing Diagram MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev MCK t DDKHMHmax DDKHMH(min) = –0.6 ns Figure 5. Timing Diagram for tDDKHMH t MCK t ,t DDKHAS DDKHCS t ,t DDKHAX DDKHCX NOOP t DDKHMP t DDKHMH t DDKHDS DDKHDX DDKHMH t DDKHME t DDKLDS t DDKLDX Freescale Semiconductor ). ...
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... MPX clock refers to the platform clock. 3. Actual attainable baud rate will be limited by the latency of interrupt processing. 4. The middle of a start bit is detected as the 8 th sampled each 16 sample. MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor = 50 Ω Figure 7. DDR AC Test Load ...
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... MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev and Table 25. The potential applied to the input of a GMII, MII, TBI, into a GMII receiver powered from a 2.5-V supply). OH Symbol Min LV 3.135 2. — 2 — — IH Max Unit 3.465 V — V 0.50 V — V 0.90 V μA 40 Freescale Semiconductor Notes 1, 2 — — — — ...
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... That is, the transmit clock must be applied to the eTSECn’s TSECn_TX_CLK, while the receive clock must be applied to pin TSECn_RX_CLK. The eTSEC internally uses the transmit MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management Symbol ...
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... FIRDX Table 27. Typ Max Unit 8.0 100 8.0 100 50 55 — 250 — 0.75 — 0.75 — — — 3.0 Typ Max Unit 8.0 100 8.0 100 50 55 — 250 — 0.75 — 0.75 — — — — Freescale Semiconductor ...
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... GMII data TXD[7:0], TX_ER, TX_EN setup time GTX_CLK to GMII data TXD[7:0], TX_ER, TX_EN delay GTX_CLK data clock rise time (20%–80%) MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management Figure 8 and Figure 9 ...
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... DD 1 Symbol 3 t GRX t /t GRXH GRX t GRDVKH t GRDXKH 2 t GRXR 1 Min Typ Max — — 1.0 symbolizes GMII GTKHDV t GTXR Min Typ Max — 8.0 — 40 — 60 2.0 — — 0.5 — — — — 1.0 Freescale Semiconductor Unit ns Unit ...
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... RXD[7:0] RX_DV RX_ER 8.2.3 MII AC Timing Specifications This section describes the MII transmit and receive AC timing specifications. MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management of 3.3 V ± 5% and 2.5 V ± 5 Symbol 2 ...
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... DD 1 Symbol 2,3 t MRX 3 t MRX t /t MRXH MRX Min Typ Max — 400 — — 40 — 35 — 1.0 — 4.0 1.0 — 4.0 symbolizes MII MTKHDX t MTXR Min Typ Max — 400 — — 40 — 35 — 65 Freescale Semiconductor Unit Unit ...
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... MII receive AC timing diagram. RX_CLK RXD[3:0] RX_DV RX_ER 8.2.4 TBI AC Timing Specifications This section describes the TBI transmit and receive AC timing specifications. MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management of 3.3 V ± 5 Symbol t MRDVKH t ...
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... TTX symbolizes the TBI transmit timing (TT) with respect to the time from t Min Typ Max Unit 2.0 — — 1.0 — — — — 1.0 — — 1.0 symbolizes the TBI TTKHDV (K) going high TTX Freescale Semiconductor ...
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... R (rise (fall). For symbols representing skews, the subscript is skew (SK) followed by the clock that is being skewed (TRX). 2. Guaranteed by design. 3. ±100 ppm tolerance on PMA_RX_CLK[0:1] frequency MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management t TTX t ...
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... Symbol 1 t TRR t t TRRH/ TRR t TRRJ t TRRR t TRRF t TRRDVKH t TRRDXKH t TRXR Valid Data t TRDXKH t TRDXKH t TRDVKH Table 34. Min Typ Max 7.5 8.0 8 — — 250 — — 1.0 — — 1.0 2.0 — — 1.0 — — Freescale Semiconductor Unit ...
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... Guaranteed by characterization 6. ±100 ppm tolerance on RX_CLK frequency. MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management Figure 18. t ...
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... RXD[8:5] RXD[3:0] RXD[7:4] t SKRGT RXD[4] RXD[9] RXDV RXERR Table 36. of 3.3 V ± 5 Symbol t RMT t /t RMTH RMT t RMTJ t RMTR t RMTF t RGT t SKRGT t SKRGT Min Typ Max Unit — 20.0 — — — 250 1.0 — 2.0 1.0 — 2.0 Freescale Semiconductor ...
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... REF_CLK duty cycle REF_CLK peak-to-peak jitter Rise time REF_CLK (20%–80%) Fall time REF_CLK (80%–20%) RXD[1:0], CRS_DV, RX_ER setup time to REF_CLK rising edge MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Ethernet: Enhanced Three-Speed Ethernet (eTSEC), MII Management of 3.3 V ± 5 Symbol ...
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... MII (M) receive (RX) clock. For rise and fall times, the latter convention Ω Figure 21. eTSEC AC Test Load t RMR t t RMRH RMRF Valid Data t RMRDV Figure 22. RMII Receive AC Timing Diagram “Section 8, “Ethernet: Enhanced Three-Speed 1 Min Typ Max 2.0 — — symbolizes MII MRDVKH clock reference MRX Ω RMRR t RMRDX Freescale Semiconductor Unit ns ...
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... MDC clock pulse width high MDC to MDIO valid MDC to MDIO delay MDIO to MDC setup time MDIO to MDC hold time MDC rise time MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Ethernet Management Interface Electrical Characteristics Table 38. Symbol Min OV 3 ...
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... For example, t from clock reference (K) high (H) until data outputs (D) are invalid (X) or data MDC = 50 Ω Figure 23. eTSEC AC Test Load NOTE t MDC t t MDCH MDCF t MDDVKH t MDDXKH t MDKHDX Typ Max Unit — symbolizes MDKHDX Ω MDCR Freescale Semiconductor Notes 4 ...
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... Local bus clock to output valid (except LAD/LDP and LALE) Local bus clock to data valid for LAD/LDP Local bus clock to address valid for LAD Local bus clock to LALE assertion MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Symbol Min V 2 ...
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... LSYNC_IN for PLL enabled or internal local bus clock for PLL = 50 Ω Figure 25. Local Bus AC Test Load 1 Min Max Unit 0.7 — ns 0.7 — ns — 2.5 ns — 2.5 ns symbolizes local bus LBIXKH1 clock reference (K) goes high (H), in this case for LBOTOT Ω L Freescale Semiconductor Notes — ...
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... Local bus duty cycle Internal launch/capture clock to LCLK delay Input setup to local bus clock (except LGTA/LUPWAIT) LGTA/LUPWAIT input setup to local bus clock Input hold from local bus clock (except LGTA/LUPWAIT) MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor t LBIVKH1 t LBIVKH2 t ...
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... Max Unit –1.3 — ns 1.5 — ns — –0.3 ns — –0.1 ns — — –3.2 — ns –3.2 — ns — 0.2 ns — 0.2 ns symbolizes local bus LBIXKH1 clock reference (K) goes high (H), in this case clock reference ( high (H), with respect of the signal DD Freescale Semiconductor Notes ...
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... LGTA/LUPWAIT signal, which is captured at the rising edge of the internal clock. MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor t LBKHKT t LBKLOV1 ...
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... UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 28. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV (clock ratio of 4) (PLL Enabled) MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev LBKHOV1 LBKHOZ1 t LBIVKH2 t LBIVKH1 t t LBKHOV1 LBKHOZ1 at clock ] t LBIXKH2 t LBIXKH1 Freescale Semiconductor ...
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... LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 29. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV (clock ratio of 4) MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor t LBKLOV1 t LBIVKH1 (PLL Bypass Mode) Local Bus ...
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... LAD[0:31]/LDP[0:3] UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 30. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV (clock ratio 16) MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev LBKHOV1 LBKHOZ1 t LBIVKH2 t LBIVKH1 t t LBKHOV1 LBKHOZ1 (PLL Enabled) t LBIXKH2 t LBIXKH1 Freescale Semiconductor ...
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... UPM Mode Input Signal: LUPWAIT Input Signals: LAD[0:31]/LDP[0:3] UPM Mode Output Signals: LCS[0:7]/LBS[0:3]/LGPL[0:5] Figure 31. Local Bus Signals, GPCM/UPM Signals for LCRR[CLKDIV (clock ratio 16) MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor t LBKLOV1 t LBIVKH1 (PLL Bypass Mode) Local Bus t ...
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... JTIVKH t JTDXKH TMS, TDI t JTIXKH t JTKLDV TDO t JTKLOV Max Unit 0.8 V μA ±5 — V 0.2 V Table 1 and Table 2. Figure 33 through Figure 35. 1 Min Max Unit Notes 0 33.3 MHz 30 — — — — 0 — — 25 — Freescale Semiconductor — — — ...
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... Figure 32. AC Test Load for the JTAG Interface Figure 33 provides the JTAG clock input timing diagram. JTAG External Clock Figure 33. JTAG Clock Input Timing Diagram MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Table 3). 2 Symbol t JTKLDX TDO ...
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... VM = Midpoint Voltage (OV DD /2) Figure 35. Boundary-Scan Timing Diagram 2 C interfaces. 2 Table 45 Electrical Characteristics of 3.3 V ± 5%. DD Symbol I2KHKL JTDXKH Input Data Valid Output Data Valid 2 C interfaces of the MPC8640. Min Max Unit 0.7 × 0 0.3 × OV –0 0.2 × Freescale Semiconductor Notes — — ...
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... Set-up time for STOP condition Bus free time between a STOP and START condition Noise margin at the LOW level for each connected device (including hysteresis) MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Electrical Characteristics (continued) of 3.3 V ± 5%. DD ...
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... C AC Test Load 1 Min Max 0.2 × OV — DD symbolizes I I2DVKH clock reference (K) going to the I2C symbolizes I I2PVKH 2 C SCL clock frequency 133 MHz 0x00 384 346 KHz 2 C Frequency Divider Ratio ) of the SCL signal. I2CL Ω L Freescale Semiconductor Unit timing 2 C clock I2C ...
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... Signal Terms Definition The SerDes utilizes differential signaling to transfer data across the serial link. This section defines terms used in the description and specification of differential signals. MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 2 C bus I2DVKH ...
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... Differential Swing, VID or VOD = A – B Differential Peak Voltage, VDIFFp = | Differential Peak-Peak Voltage, VDIFFpp = 2 × VDIFFp (not shown) (or Differential Output Swing): OD (or Differential Input Swing ÷ defined as the OD – V The SDn_TX SDn_TX defined as the ID – The SDn_RX SDn_RX = |A – B| volts. DIFFp Freescale Semiconductor ...
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... SDn_REF_CLK for PCI Express and Serial RapidIO. The following sections describe the SerDes reference clock requirements and some application information. MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor = 2 × × |(A – B)| volts, which is twice of differential swing in DIFFp Figure example for differential waveform ...
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... The input amplitude requirement — This requirement is described in detail in the following sections _REF_CLK SD n _REF_CLK Figure 39. Receiver of SerDes Reference Clocks MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev SRDSn are specified in Table 1 DD_ 50 W Input Amp 50 W and Table 2. Freescale Semiconductor ...
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... Input Amplitude or Differential Peak < 800mV SD n _REF_CLK SD n _REF_CLK Figure 40. Differential Reference Clock Input DC Requirements (External DC-Coupled) MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Figure 40 shows the SerDes reference clock input requirement Figure 41 shows the SerDes reference clock input ...
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... LVPECL outputs can produce signal with too large amplitude. It may need to be DC-biased at clock driver output first and followed with series attenuation resistor to reduce the amplitude, in addition to AC-coupling. MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev Vmax < Vcm + 400 mV Vcm Vmin > Vcm – 400 Freescale Semiconductor ...
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... They may also vary from one vendor to the other. Therefore, Freescale Semiconductor can neither provide the optimal clock driver reference circuits, nor guarantee the correctness of the following clock driver connection reference circuits ...
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... For example, if the LVPECL output’s differential peak is 900 mV and the desired SerDes reference clock input amplitude is selected as 600 mV, the attenuation factor is 0.67, which requires Ω. MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev _REF_CLK 100 Ω differential PWB trace SD n _REF_CLK MPC8640D 50 Ω SerDes Refer. CLK Receiver 50 Ω Figure 45 Freescale Semiconductor ...
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... Phase noise less than 100 kHz can be tracked by the PLL and data recovery loops and is less of a problem. Phase noise above 15 MHz is filtered by the PLL. The most problematic phase noise MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor SD n _REF_CLK 10nF ...
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... MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev SRDS1 or XV SRDS2 = 1.1 V ± 5% and 1.05 V ± 5%. DD_ DD_ Symbol Rise Edge Rate Fall Edge Rate Rise-Fall Matching Figure 47. Figure 48. Min Max Unit Notes 1.0 4.0 V/ 1.0 4.0 V/ +200 — — –200 mV 2 — Freescale Semiconductor ...
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... Section 15, “Serial RapidIO” Note that external AC Coupling capacitor is required for the above two serial transmission protocols with the capacitor value defined in specification of each protocol section. MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor SD n _REF_CLK SD n _REF_CLK SD1_RX n or ...
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... Each UI is 400 ps ± 300 ppm. UI does not account for spread spectrum clock dictated variations. See Note 1. 0.8 — 1 TX-DIFFp-p Min Typical Max Units Notes — 10 — ns — — 100 ps –50 — Notes = 2 × |V – See Note 2. TX-D+ TX-D- Freescale Semiconductor — — — ...
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... Voltage Tx Short Circuit I TX-SHORT Current Limit Minimum time T TX-IDLE-MIN spent in electrical idle MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Min Nom Max Units –3.0 –3.5 –4.0 dB Ratio of the V after a transition divided by the V bit after a transition. See Note 2. ...
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... See Note 7. TX-EYE-MEDIAN-to-MAX-JITTER built-in. An external AC coupling capacitor is required. TX Notes Figure 52 and measured over Figure 50) = 0.30 UI for the TX-JITTER-MAX median is less than half of the total Figure 52). Note that the series capacitors Figure 52 for both V and V TX-D+ TX-D– Freescale Semiconductor . ...
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... UI interval with a fit algorithm using a minimization merit function (that is, least squares and median deviation fits). Figure 50. Minimum Transmitter Timing and Voltage Output Compliance Specifications MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor is specified using the passive compliance/test measurement load (see NOTE PCI Express ...
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... Rx DC Differential mode impedance. See Note 5 Required well as D– DC impedance (50 ± 20% tolerance). See Notes 2 and 5. Required well as D– DC impedance when the receiver terminations do not have power. See Note × –V RX-IDLE-DET-DIFFp-p RX-D+ RX-D– Measured at the package pins of the receiver Freescale Semiconductor = |/2 | ...
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... PCI Express component to vary in impedance from the compliance/test measurement load. The input receiver eye diagram is implementation specific and is not specified component designer should provide MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Min Nom Max Units — ...
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... Figure 51. Minimum Receiver Eye Timing and Voltage Compliance Specification MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev NOTE Figure 52). Note that the series capacitors, C Ω to ground for , are TX Freescale Semiconductor ...
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... All unit intervals are specified with a tolerance of ± 100 ppm. The worst case frequency difference between any transmit and receive clock will be 200 ppm. MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Figure 52. NOTE ...
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... MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev Min Typical Max Units — 10(8) — — — 80 –40 — 40 Figure 53 shows how the signals are defined. The figures show , is defined defined Comments applies only to serial RapidIO with 125-MHz reference clock ps — ps — – – Freescale Semiconductor ...
Page 77
... XAUI has similar application goals to the serial RapidIO interface. The goal of this standard is that electrical designs for the serial RapidIO interface can reuse electrical designs for XAUI, suitably modified for applications at the baud intervals and reaches described herein. MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Differential Peak-Peak = 2 * (A-B) Serial RapidIO 77 ...
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... UI p-p — UI p-p — ps Skew at the transmitter output between lanes of a multilane link ps ± 100 ppm Unit Notes Volts Voltage relative to COMMON of either signal comprising a differential pair mV p-p — UI p-p — UI p-p — Freescale Semiconductor ...
Page 79
... Table 55. Long Run Transmitter AC Timing Specifications—1.25 GBaud Parameter Output Voltage, Differential Output Voltage Deterministic Jitter Total Jitter Multiple output skew Unit Interval MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Range Symbol Min Max S — 1000 MO UI ...
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... Unit Notes Volts Voltage relative to COMMON of either signal comprising a differential pair mV p-p — UI p-p — UI p-p — ps Skew at the transmitter output between lanes of a multilane link ps ± 100 ppm Table 58 when measured at the Freescale Semiconductor ...
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... MHz to (0.8) × (Baud Frequency). This includes contributions from on-chip circuitry, the chip package and any off-chip components related to the receiver. AC-coupling MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor A B Time in UI ...
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... Figure 55. The sinusoidal jitter component Unit Notes mV p-p Measured at receiver UI p-p Measured at receiver UI p-p Measured at receiver UI p-p Measured at receiver ns Skew at the receiver input between lanes of a multilane link — — ps ± 100 ppm Figure 55. The sinusoidal jitter component Freescale Semiconductor ...
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... MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Range Symbol Min ...
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... Serial RapidIO Figure 55 shows the single frequency sinusoidal jitter limits. 8.5 UI p-p Sinusoidal Jitter Amplitude 0.10 UI p-p 22.1 kHz Figure 55. Single Frequency Sinusoidal Jitter Limits MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev 1.875 MHz 20 MHz Frequency Freescale Semiconductor ...
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... Table 62. Receiver Input Compliance Mask Parameters Exclusive of Sinusoidal Jitter Receiver Type 1.25 GBaud 2.5 GBaud 3.125 GBaud MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor (Table 59 through Table Table 62. The eye pattern of the receiver test signal is measured A ...
Page 86
... Eye template measurement requirements are as defined above. MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev Section 15.7, “Receiver Specifications,” Figure 56 and Table 62. Note that for this to occur, the test signal -12 . Freescale Semiconductor ...
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... Maximum module height Minimum module height Solder Balls 2 Ball diameter (typical ) 1 High-coefficient of thermal expansion 2 Typical ball diameter is before reflow MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Section 15.7, “Receiver 12.1 mm × 14 × 1023 caps; 100 nF each 1 HX) 2. ...
Page 88
... The mechanical dimensions and bottom surface nomenclature of the MPC8640D (dual core) and MPC8640 (single core) high-lead FC-CBGA (package option: HCTE HX) and lead-free FC-CBGA (package option: HCTE VU) are shown respectfully in Figure 57. MPC8640D High-Lead FC-CBGA Dimensions MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev Figure 57 and Figure 58. Freescale Semiconductor ...
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... VDD_Core1 (R16, R18, R20, T17, T19, T21, T23, U16, U18, U22, V17, V19, V21, V23, W16, W18, W20, W22, Y17, Y19, Y21, Y23, AA16, AA18, AA20, AA22, AB23, AC24) and SENSEVDD_Core1 (U20). MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor NOTES for Figure 57 ...
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... Package Figure 58. MPC8640D Lead-Free FC-CBGA Dimensions MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev Freescale Semiconductor ...
Page 91
... AC10 D1_MCS[0:3] AB9, AD10, AC12, AD11 D1_MCKE[0:3] P7, M10, N8, M11 D1_MCK[0:5] W6, E13, AH11, Y7, F14, AG10 MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor NOTES for Figure 58 Package Pin Number DDR Memory Interface 1 Signals Signal Listings Pin Type Power Supply ...
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... D2_GV DD O D2_GV DD O D2_GV DD O D2_GV DD O D2_GV DD O D2_GV DD O D2_GV DD IO D2_GV DD D2_GV /2 DD reference voltage Freescale Semiconductor Notes — — — — — — — — — — — — — 23 — — — — — — ...
Page 93
... H30, R32, V28, AG32 Reserved H29, R31, W28, AG31 Reserved AD24, AG26 MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Package Pin Number High Speed I/O Interface 2 (SERDES 2) Special Connection Requirement pins Ethernet Miscellaneous Signals Signal Listings Pin Type ...
Page 94
... TSEC2_RX_DV AC19 TSEC2_RX_ER AD21 MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev Package Pin Number 5 eTSEC Port 1 Signals 5 eTSEC Port 2 Signals Pin Type Power Supply I I 6,10 I Freescale Semiconductor Notes 39 39 — — — — 10 — — — 10 — — ...
Page 95
... TSEC4_RXD[0:7] AG14, AD13, AF13, AD14, AE14, AB15, AC14, AE17 TSEC4_RX_DV AC15 TSEC4_RX_ER AF14 TSEC4_RX_CLK AG13 MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Package Pin Number 5 eTSEC Port 3 Signals 5 eTSEC Port 4 Signals Signal Listings Pin Type Power Supply I ...
Page 96
... D32, F30 DMA_DACK[2]/LCS[6] E23 DMA_DACK[3]/IRQ[10] C30 MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev Package Pin Number 5 Local Bus Signals 5 DMA Signals Pin Type Power Supply Freescale Semiconductor Notes — — — — — — — — — ...
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... L16 SRESET_0 C20 SRESET_1 C21 CKSTP_IN L18 CKSTP_OUT L17 READY/TRIG_OUT J13 MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Package Pin Number Programmable Interrupt Controller Signals 5 DUART Signals Signals System Control Signals Signal Listings Pin Type Power Supply ...
Page 98
... MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev Package Pin Number 5 Debug Signals Power Management Signals System Clocking Signals 5 Test Signals 5 JTAG Signals 5 Miscellaneous Pin Type Power Supply — — Freescale Semiconductor Notes — — 10 — — — — ...
Page 99
... F26, F29, G17, H21, H24, K19, K23, M21, AM30 LV AC20, AD23, AH22 DD TV AC17, AG18, AK20 DD MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Package Pin Number Additional Analog Signals Sense, Power and GND Signals V DD sensing pin V DD ...
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... DD_ 1.05/1.1 V Port 2 V _Core0 DD supply 0.95/1.05/1 _Core1 12 supply 0.95/1.05/1 _PLAT DD voltage 1.05/1 _Core0 DD Supply 0.95/1.05/ 1 _Core1 DD Supply 0.95/1.05/ 1 _PLAT DD 1.05/1 _LB DD 1.05/1 _SRDS1 DD 1.05/1 _SRDS2 DD 1.05/1.1 V Freescale Semiconductor Notes — — — — — — — — — ...
Page 101
... TSEC2_TXD[0:3]/ AB20, AJ23, AJ22, AD19 cfg_rom_loc[0:3] TSEC2_TXD[4], AH23, TSEC2_TX_ER/ AB19 cfg_dram_type[0:1] MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Package Pin Number SerDes Port 1 Ground pin for AV SerDes Port 2 Ground pin for AV Ground pins for Ground pins for ...
Page 102
... Package Pin Number Pin Type Power Supply — — — — — — — — — — — — — — — — — Freescale Semiconductor Notes — — 33 — — — — — — — — — — — — — — ...
Page 103
... Used as serial data input for serial RapidIO 1×/4× link. 36.This pin requires an external 4.7-kΩ pull-down resistor to prevent PHY from seeing a valid transmit enable before it is actively driven. MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Package Pin Number . DD ...
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... Min 800 1000 800 Pin Type Power Supply _Core1 should be pulled to ground with a weak Table 65 provides the clocking 1250MHz Unit Max Min Max 1067 800 1250 MHz and Section 18.3, “e600 to MPX clock PLL Ratio,” Freescale Semiconductor Notes Table 67 Notes 1, 2 ...
Page 105
... The MPX clock is the clock that drives the MPX bus, and is also called the platform clock. The frequency of the MPX is set using the following reset signals, as shown in • SYSCLK input signal MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Maximum Processor Core Frequency 1000, 1067, 1250 MHz Min ...
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... Reserved 1000 8:1 1001 Reserved Table 69. e600 Core to MPX Clock Ratio Binary Value of e600 core: MPX Clock Ratio 01000 01100 2.5:1 10000 11100 Reserved 10100 Reserved 01110 Reserved 2:1 3:1 Freescale Semiconductor ...
Page 107
... For example, if the platform frequency is 500 MHz, the FIFO Tx/Rx clock frequency should be no more than 156 MHz. 19 Thermal This section describes the thermal specifications of the MPC8640. MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Section 17, “Signal Listings,” SYSCLK (MHz ...
Page 108
... MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 108 Table 71. Package Thermal Characteristics Section 19.2.4, “Temperature Diode,” 1 Symbol Value Unit Notes R 18 °C θ °C θ °C θ JMA R 9 °C θ JMA R 5 °C/W 4 θ < 0.1 °C/W 5 θ JC for more Figure 59 shows a spring Freescale Semiconductor ...
Page 109
... Alhambra Road, Suite 1 Warwick, RI 02886 Internet: www.calgreg.com International Electronic Research Corporation (IERC)818-842-7277 413 North Moss St. Burbank, CA 91502 Internet: www.ctscorp.com MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor HCTE FC-CBGA Package Heat Sink Heat Sink Clip Thermal Printed-Circuit Board 603-224-9988 ...
Page 110
... Figure 60. C4 Package with Heat Sink Mounted to a Printed-Circuit Board MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 110 408-436-8770 800-522-6752 603-635-5102 Table 71, the intrinsic conduction thermal Radiation Convection Heat Sink Printed-Circuit Board Radiation Convection Thermal Interface Material Die/Package Die Junction Package/Leads Freescale Semiconductor ...
Page 111
... Figure 61. Thermal Performance of Select Thermal Interface Material MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Silicone Sheet (0.006 in.) Bare Joint Fluoroether Oil Sheet (0.007 in.) Graphite/Oil Sheet (0.005 in.) Synthetic Grease ...
Page 112
... R is the heat sink base-to-ambient thermal resistance θ the power dissipated by the device d MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 112 800-347-4572 781-935-4850 800-248-2481 888-642-7674 888-246-9050 ) × θJC θint θsa d Freescale Semiconductor ...
Page 113
... K) in the xy-plane and 9.6 W/(m • the z-direction. An LGA solder layer would be modeled as a collapsed thermal resistance with thermal conductivity of 9.6W/(m • K) and an effective height of 0.1 mm. MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor ) should be maintained less than the value specified ° ...
Page 114
... W/(m • K) 13.5 W/(m • K) 13.5 5.3 0.034 W/(m • K) 0.034 y 9.6 variation of each MPC8640’s internal diode. BE 0.9% ± Die Bump and Underfill z Substrate C5 solder layer Side View of Model (Not to Scale) x Substrate Die Top View of Model (Not to Scale) Freescale Semiconductor ...
Page 115
... The above simplifies to the following –4 = 1.986 × 10 × – Solving for T, the equation becomes: V – __________ nT = –4 1.986 × 10 MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor is flowing H is flowing L –19 C) –23 Joules/K) Thermal 115 ...
Page 116
... MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 116 Section 18.2, “MPX to SYSCLK PLL Ratio.” is provided with power through independent AV DD 2.2 µF 2.2 µF Low ESL Surface Mount Capacitors GND Figure 64, one to each of the type pin being supplied to minimize DD _PLAT, AV _LB; DD Freescale Semiconductor DD ...
Page 117
... This noise must be prevented from reaching other components in the MPC8640 system, and the device itself requires a clean, tightly regulated source of power. Therefore recommended that the system MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor AV DD 2.2 µF 2.2 µ ...
Page 118
... MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 118 , Dn_GV _Coren, and V _PLAT and GND power planes in the PCB _Coren, and _SRDSn, and SV as required and unused active high inputs should _Coren _PLAT planes, to enable quick DD and XV _SRDSn) to ensure Dn_GV , Freescale Semiconductor ...
Page 119
... DEVDISR. See Note 1 for more information. If the high-speed SerDes port requires complete or partial termination, the unused pins should be terminated as described in this section. MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Section 20.5.1, “Guidelines for High-Speed Interface Table 72 describes the possible enabled/disabled scenarios ...
Page 120
... MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 120 NOTE Section 17, “Signal Listings.” (100Ω –1 kΩ Ω resistor: SD1_IMP_CAL_TX, Ω pull down resistor to prevent PHY from seeing a valid _Core1 which exist on the DD DD (2–10 kΩ) to their Ω resistor: Freescale Semiconductor ...
Page 121
... The driver impedances are targeted at minimum V , 105 °C. nominal OV DD Impedance Configuration, Power Note: Nominal supply voltages. See MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 2 C). is trimmed until the voltage at the pad equals P ) ÷ Pad Data ...
Page 122
... COP reset signals must be merged into these signals with logic. The arrangement shown in Figure 67 while ensuring that the target can drive HRESET as well. MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 122 allows the COP port to independently assert HRESET or TRST, Freescale Semiconductor ...
Page 123
... No connection is required for TDI, TMS, or TDO. COP_SRESET COP_HRESET COP_CHKSTP_OUT MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Figure 67, for connection to the target system, and is Figure 68, can be duplicated for each processor. The Figure 69. Please consult with your tool vendor to ...
Page 124
... COP_SRESET 5 COP_TRST 10 Ω 2 COP_VDD_SENSE NC COP_CHKSTP_OUT 10 kΩ COP_CHKSTP_IN COP_TMS COP_TDO COP_TDI COP_TCK 10 kΩ kΩ SRESET0 10 kΩ SRESET1 1 10 kΩ HRESET 10 kΩ 10 kΩ 10 kΩ 10 kΩ 1 TRST CKSTP_OUT 10 kΩ CKSTP_IN TMS TDO TDI TCK Freescale Semiconductor ...
Page 125
... Although pin 12 is defined as a No-Connect, some debug tools may use pin additional GND pin for improved signal integrity. Figure 69. JTAG/COP Interface Connection for Multiple MPC8640 Devices in Daisy Chain Configuration MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor OV DD 10kΩ ...
Page 126
... Core DDR speed Product Revision Level 2 (MHz) (MHz) Revision C = 2.1 System Version Register Value for Rev C: 0x8090_0021 MPC8640 533 MHz 0x8090_0121 MPC8640D 1250 H = 500 MHz Revision E = 3.0 System Version Register Value for Rev E: 0x8090_0030 MPC8640 0x8090_0130 MPC8640D _PLAT = 1. Freescale Semiconductor z ...
Page 127
... Note that the “w” represents the operating temperature range. The “xx” in the part marking represents the package option. The “z” represents the product revision level. For more information see MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor 1 Operating Conditions ...
Page 128
... MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 128 Figure 70. MC8640x xxnnnnxx TWLYYWW MMMMMM YWWLAZ Table 76. Document Revision History Substantive Change(s) 74, “Part Numbering Nomenclature,” and 5, “MPC8640D Individual Supply Maximum Power Dissipation 1.” Table 49, “Differential Transmitter Output Specifications.” 8640D Table 75, “Part Offerings and Operating Freescale Semiconductor ...
Page 129
... Removed the part offering MC8640Dwxx1000NC which is replaced with MC8640Dwxx1067NC and removed MC8640wxx1000NC replaced with MC8640wxx1067NC in • Added Note 07/2008 • Initial Release MPC8640 and MPC8640D Integrated Host Processor Hardware Specifications, Rev. 3 Freescale Semiconductor Table 76. Document Revision History Substantive Change(s) Table 2 because it is not supported by MPC8640D or MPC8640 and Table 6 with the new 1067/533 MHz device offering. This includes updated Power SDRAM” ...
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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...